From 38e9d5afd096004e9b3b1494d02641cb76d60b7a Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <maltanar@gmail.com>
Date: Wed, 1 Feb 2023 11:21:23 +0100
Subject: [PATCH] [FIFO] use impl_style=hls for first&last FIFOs to avoid
glitch
---
.../fpgadataflow/insert_fifo.py | 20 ++++++-------------
.../fpgadataflow/set_fifo_depths.py | 7 ++++++-
2 files changed, 12 insertions(+), 15 deletions(-)
diff --git a/src/finn/transformation/fpgadataflow/insert_fifo.py b/src/finn/transformation/fpgadataflow/insert_fifo.py
index 50da9cdf1..bfeee95e9 100644
--- a/src/finn/transformation/fpgadataflow/insert_fifo.py
+++ b/src/finn/transformation/fpgadataflow/insert_fifo.py
@@ -209,13 +209,9 @@ class InsertFIFO(Transformation):
graph.value_info.append(fifo_output_tensor)
model.set_tensor_datatype(fifo_output_tensor.name, dtype)
- if (
- self.max_qsrl_depth is None
- or fifo_depth <= self.max_qsrl_depth
- ):
- impl_style = "rtl"
- else:
- impl_style = "vivado"
+ # only use rtl-style FIFOs to avoid simulation bug
+ # (top-level IOs should not have impl_style=vivado)
+ impl_style = "rtl"
fifo_node = oh.make_node(
"StreamingFIFO",
@@ -271,13 +267,9 @@ class InsertFIFO(Transformation):
graph.value_info.append(fifo_input_tensor)
model.set_tensor_datatype(fifo_input_tensor.name, dtype)
- if (
- self.max_qsrl_depth is None
- or fifo_depth <= self.max_qsrl_depth
- ):
- impl_style = "rtl"
- else:
- impl_style = "vivado"
+ # only use rtl-style FIFOs to avoid simulation bug
+ # (top-level IOs should not have impl_style=vivado)
+ impl_style = "rtl"
fifo_node = oh.make_node(
"StreamingFIFO",
diff --git a/src/finn/transformation/fpgadataflow/set_fifo_depths.py b/src/finn/transformation/fpgadataflow/set_fifo_depths.py
index 2619557ed..35e7b9e6c 100644
--- a/src/finn/transformation/fpgadataflow/set_fifo_depths.py
+++ b/src/finn/transformation/fpgadataflow/set_fifo_depths.py
@@ -412,8 +412,13 @@ class InsertAndSetFIFODepths(Transformation):
node_inst = getCustomOp(node)
node_inst.set_nodeattr("depth", depth)
node_inst.set_nodeattr("depth_monitor", 0)
+ # exception for top-level IO FIFOs which cause a bug in simulation
+ # (top-level IOs should not have impl_style=vivado)
+ toplevel_in = node.input[0] in [x.name for x in model.graph.input]
+ toplevel_out = node.output[0] in [x.name for x in model.graph.output]
+ toplevel_style_exception = toplevel_in or toplevel_out
# Set FIFO implementation/ram styles
- if depth > self.max_qsrl_depth:
+ if (depth > self.max_qsrl_depth) and (not toplevel_style_exception):
node_inst.set_nodeattr("impl_style", "vivado")
node_inst.set_nodeattr("ram_style", self.vivado_ram_style)
else:
--
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