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Commit 174f6f32 authored by Georg Streich's avatar Georg Streich
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Add control port

parent ac533565
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......@@ -22,7 +22,7 @@ np.save(open("expected_output.npy", "wb"), out)
model_dir = os.environ['FINN_ROOT'] + "/notebooks/end2end_example/cybersecurity"
model_file = model_dir + "/cybsec-mlp-ready.onnx"
estimates_output_dir = "output_estimates_only"
estimates_output_dir = "command_after_loop"
os.environ["RTLSIM_TRACE_DEPTH"] = "3"
......@@ -41,7 +41,7 @@ steps = [
"step_generate_estimate_reports",
"step_hls_codegen",
"step_hls_ipgen",
"step_set_fifo_depths",
# "step_set_fifo_depths",
"step_create_stitched_ip",
]
......
......@@ -224,7 +224,7 @@ class ACCLOut(ACCLOp):
'#pragma HLS INTERFACE axis port=in0_{}'.format(self.hls_sname()),
"#pragma HLS INTERFACE s_axilite port=dpcfg_adr bundle=control",
"#pragma HLS INTERFACE s_axilite port=comm_adr bundle=control",
"#pragma HLS INTERFACE ap_ctrl_none port=return",
"#pragma HLS INTERFACE s_axilite port=return bundle=control",
]
def strm_decl(self):
......
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