Fix bug

custom_hls/accl/funcs.hpp

@@ -19,7 +19,6 @@ void accl_out(
 ) {
     STREAM<stream_word> data_from_cclo;
 
-    accl_hls::ACCLCommand accl(cmd_to_cclo, sts_from_cclo, comm_adr, dpcfg_adr, 0, 3);
     accl_hls::ACCLData data(data_to_cclo, data_from_cclo);
 
     ap_uint<accl_width> accl_word;
@@ -51,6 +50,7 @@ void accl_out(
         data.push(accl_word, 0);
     }
 
+    accl_hls::ACCLCommand accl(cmd_to_cclo, sts_from_cclo, comm_adr, dpcfg_adr, 0, 3);
     accl.stream_put(num_transfer_bits / 32, 9, destination, 0, false);
 
 #ifdef CPPSIM

notebooks/end2end_example/cybersecurity/build_accl.py

@@ -5,28 +5,35 @@ import numpy as np
 import finn.builder.build_dataflow as build
 import finn.builder.build_dataflow_config as build_cfg
 
-inp = np.zeros((1, 3, 32, 32)).astype(np.float32)
-out = np.zeros((1)).astype(np.float32)
+unsw_nb15_data = np.load("./unsw_nb15_binarized.npz")
+
+inp = unsw_nb15_data["train"][:, :-1]
+inp = np.concatenate([inp, np.zeros((inp.shape[0], 7))], -1).astype(np.float32)
+out = unsw_nb15_data["train"][:, -1].astype(np.float32)
+
+indices = np.where(out == 0)[0][:1]
+
+inp = 2 * inp[indices] - 1
+out = 2 * out[indices] - 1
 
 np.save(open("input.npy", "wb"), inp)
 np.save(open("expected_output.npy", "wb"), out)
 
-
-model_dir = os.environ['FINN_ROOT'] + "/pretrained_models"
-model_file = model_dir + "/end2end_cnv_w1a1_folded.onnx"
+model_dir = os.environ['FINN_ROOT'] + "/notebooks/end2end_example/cybersecurity"
+model_file = model_dir + "/cybsec-mlp-ready.onnx"
 
 estimates_output_dir = "output_estimates_only"
 
 os.environ["RTLSIM_TRACE_DEPTH"] = "3"
 
 steps = [
-    # "step_qonnx_to_finn",
-    # "step_tidy_up",
-    # "step_streamline",
-    # "step_convert_to_hls",
-    # "step_create_dataflow_partition",
-    # "step_target_fps_parallelization",
-    # "step_apply_folding_config",
+    "step_qonnx_to_finn",
+    "step_tidy_up",
+    "step_streamline",
+    "step_convert_to_hls",
+    "step_create_dataflow_partition",
+    "step_target_fps_parallelization",
+    "step_apply_folding_config",
     "step_minimize_bit_width",
     "step_assign_partition_ids",
     "step_insert_accl",
@@ -42,8 +49,8 @@ cfg_splits = build.DataflowBuildConfig(
     verbose             = True,
     output_dir          = estimates_output_dir,
     steps               = steps,
-    # mvau_wwidth_max     = 64,
-    # target_fps          = 1000000,
+    mvau_wwidth_max     = 80,
+    target_fps          = 1000000,
     synth_clk_period_ns = 10.0,
     generate_outputs    = [
         build_cfg.DataflowOutputType.ESTIMATE_REPORTS,
@@ -54,8 +61,8 @@ cfg_splits = build.DataflowBuildConfig(
     shell_flow_type     = build_cfg.ShellFlowType.VITIS_ALVEO,
     board               = "U55C",
     num_boards          = 2,
+    # start_step="step_create_stitched_ip",
     save_intermediate_models = True,
-    # start_step="step_insert_accl",
 )
 
 build.build_distributed_dataflow_cfg(model_file, cfg_splits)

src/finn/custom_op/fpgadataflow/accl.py

@@ -224,6 +224,7 @@ class ACCLOut(ACCLOp):
             '#pragma HLS INTERFACE axis port=in0_{}'.format(self.hls_sname()),
             "#pragma HLS INTERFACE s_axilite port=dpcfg_adr bundle=control",
             "#pragma HLS INTERFACE s_axilite port=comm_adr bundle=control",
+            "#pragma HLS INTERFACE ap_ctrl_none port=return",
         ]
 
     def strm_decl(self):