[Infra] memstream path bugfix

src/finn/transformation/fpgadataflow/create_stitched_ip.py

@@ -230,7 +230,7 @@ class CreateStitchedIP(Transformation):
         model = model.transform(ReplaceVerilogRelPaths())
         ip_dirs = ["list"]
         # add RTL streamer IP
-        ip_dirs.append("$::env(FINN_ROOT)/finn/finn-rtllib/memstream")
+        ip_dirs.append("$::env(FINN_ROOT)/finn-rtllib/memstream")
         if model.graph.node[0].op_type not in ["StreamingFIFO", "IODMA"]:
             warnings.warn(
                 """First node is not StreamingFIFO or IODMA.

src/finn/transformation/fpgadataflow/make_zynq_proj.py

@@ -68,7 +68,7 @@ def collect_ip_dirs(model, ipstitch_path):
     ip_dirs += [ipstitch_path + "/ip"]
     if need_memstreamer:
         # add RTL streamer IP
-        ip_dirs.append("$::env(FINN_ROOT)/finn/finn-rtllib/memstream")
+        ip_dirs.append("$::env(FINN_ROOT)/finn-rtllib/memstream")
     return ip_dirs