From 0a78e95631c2746c224181eb800f85a7ff620e01 Mon Sep 17 00:00:00 2001
From: Yaman Umuroglu <yamanu@xilinx.com>
Date: Fri, 13 May 2022 12:43:04 +0200
Subject: [PATCH] [Infra] memstream path bugfix
---
src/finn/transformation/fpgadataflow/create_stitched_ip.py | 2 +-
src/finn/transformation/fpgadataflow/make_zynq_proj.py | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/finn/transformation/fpgadataflow/create_stitched_ip.py b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
index b19ef170f..1f53ffd42 100644
--- a/src/finn/transformation/fpgadataflow/create_stitched_ip.py
+++ b/src/finn/transformation/fpgadataflow/create_stitched_ip.py
@@ -230,7 +230,7 @@ class CreateStitchedIP(Transformation):
model = model.transform(ReplaceVerilogRelPaths())
ip_dirs = ["list"]
# add RTL streamer IP
- ip_dirs.append("$::env(FINN_ROOT)/finn/finn-rtllib/memstream")
+ ip_dirs.append("$::env(FINN_ROOT)/finn-rtllib/memstream")
if model.graph.node[0].op_type not in ["StreamingFIFO", "IODMA"]:
warnings.warn(
"""First node is not StreamingFIFO or IODMA.
diff --git a/src/finn/transformation/fpgadataflow/make_zynq_proj.py b/src/finn/transformation/fpgadataflow/make_zynq_proj.py
index 0b92f1777..0ad1eebdd 100644
--- a/src/finn/transformation/fpgadataflow/make_zynq_proj.py
+++ b/src/finn/transformation/fpgadataflow/make_zynq_proj.py
@@ -68,7 +68,7 @@ def collect_ip_dirs(model, ipstitch_path):
ip_dirs += [ipstitch_path + "/ip"]
if need_memstreamer:
# add RTL streamer IP
- ip_dirs.append("$::env(FINN_ROOT)/finn/finn-rtllib/memstream")
+ ip_dirs.append("$::env(FINN_ROOT)/finn-rtllib/memstream")
return ip_dirs
--
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