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# Copyright (c) 2022 Xilinx, Inc.
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# * Redistributions of source code must retain the above copyright notice, this
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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import pytest
import json
import shutil
from brevitas.export.onnx.generic.manager import BrevitasONNXManager
import finn.builder.build_dataflow as build
import finn.builder.build_dataflow_config as build_cfg
from finn.util.basic import make_build_dir
from finn.util.test import get_trained_network_and_ishape
def fetch_test_model(topology, wbits=2, abits=2):
tmp_output_dir = make_build_dir("build_fifosizing_%s_" % topology)
(model, ishape) = get_trained_network_and_ishape(topology, wbits, abits)
chkpt_name = tmp_output_dir + "/model.onnx"
BrevitasONNXManager.export(model, ishape, chkpt_name)
return tmp_output_dir
@pytest.mark.slow
@pytest.mark.vivado
def test_fifosizing_linear():
tmp_output_dir = fetch_test_model("tfc")
cfg = build_cfg.DataflowBuildConfig(
output_dir=tmp_output_dir,
auto_fifo_depths=True,
auto_fifo_strategy="characterize",
target_fps=10000,
synth_clk_period_ns=10.0,
board="Pynq-Z1",
shell_flow_type=build_cfg.ShellFlowType.VIVADO_ZYNQ,
generate_outputs=[
build_cfg.DataflowOutputType.ESTIMATE_REPORTS,
build_cfg.DataflowOutputType.STITCHED_IP,
build_cfg.DataflowOutputType.RTLSIM_PERFORMANCE,
],
default_mem_mode=build_cfg.ComputeEngineMemMode.DECOUPLED,
build.build_dataflow_cfg(tmp_output_dir + "/model.onnx", cfg)
with open(tmp_output_dir + "/report/estimate_network_performance.json") as f:
est_data = json.load(f)
with open(tmp_output_dir + "/report/rtlsim_performance.json") as f:
sim_data = json.load(f)
assert (
float(sim_data["throughput[images/s]"])
/ float(est_data["estimated_throughput_fps"])
> 0.9
)
shutil.rmtree(tmp_output_dir)