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Created with Raphaël 2.2.011Sep1095432131Aug30282725242321201918171312111076543131Jul29282724222120171411109876532129Jun28272625242322211918171514121110985[Test] change k settings for test_topk_insert[Test] fix test streamline fc for new FC nets[Refactor] remove explicit calls to DoubleToSingleFloat[Core] execute DoubleToSingleFloat prior to transforms[Transformation] comment + check empty name in GiveReadableTensorNames[Test] fix debug test w Double2SingleFloat, higher atol[Deps] update Brevitas[Docs] add missing hw build img[Docs] update docs to reflect new hw build system[Refactor] ReplaceVerilogRelPaths called automatically[Notebook] all tfc notebooks now working[Transform] always call ReplaceVerilogRelPaths before PrepareRTLSim[Test] try both decoupled and const mem_mode in stitch test[StreamingFC] bring back IPI codegen for mem_mode=const -- ouchie[Refactor] remove references to old "zynq" platform[PYNQ, Test] remove old PYNQ build method and tests for it[Deps] remove PYNQ-HelloWorld[Notebook] update end2end notebooks to use ZynqBuild[Test] add rtlsim throughput test to end2end[Test] add hw throughput test to end2end testMerge branch 'dev' into feature/cleanup_end2end_and_buildMerge pull request #209 from quetric/optimize_streamerUsing list tiling instead of np.tile to avoid conversion to floatAdded debug flag to vitis builds - adds chipscope to ALL kernel interfacesUpdate out bitwidth saturation type[fpgadataflow] Fix tensor element bitwidth missmatch for labelselect_batch and channelwise_op_batchFixed rtlsim (node-by-node and stitched) for decoupled memories[Test] bring back test markers into end2end[Driver] don't use cacheable for Alveo driver[Refactor] move some functions to test utils[Test] remove individual zynq/vitis end2end tests[Test] bring Alveo/Vitis into end2end testMerge branch 'dev' into feature/cleanup_end2end_and_build[Notebook] fix broken notebooks due to unescaped "s[Test] use analysis pass info to set LIVENESS_THRESHOLD[Analysis] clarify critical_path_cycles[Core] save rtlsim sdp model after exec[Analysis] introduce dataflow_performance to extract key perf info[Test] make end2end rtlsim trace optional[Test] bring back more steps into new end2end test flow