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Created with Raphaël 2.2.020Aug1918171312111076543131Jul29282724222120171411109876532129Jun2827262524232221191817151412111098543228May2726252422[Test] add throughput tests for zynqbuild too[Core] work on making remote exec/thr test on Alveo tooMerge branch 'dev' into feature/alveo_deploy[Docker] install XRT deps[ZYNQ] use prefixes in ZynqBuild for correct resources[Transform] allow prefixes in GiveUniqueNodeNamesMerge branch 'dev' into feature/alveo_deploy[PYNQ] make deployment work for VitisBuild tooMerge pull request #217 from Xilinx/feature/prebuilt_netron[Deps] pip install netron, spec versions for all Python pkgs[Test] add end2end tfc-w1a1 test for VitisBuild[PYNQ] use metadata_prop bitfile for both Vitis and ZynqMerge branch 'dev' of https://github.com/Xilinx/finn into dev[Test] print post-synth res from all end2end testsMerge pull request #215 from Xilinx/feature/post_transform_cleanups[Test] add "full" option to quicktest.sh[Test] fix test_convert_to_hls_layers[Transform] fix MergeONNXModels after revealed bugs[StreamingFC] fix broken DataType name in default accDataType[ModelWrapper] introduce cleanup function, call in partitions too[StreamingFC] ensure 8-bit divisible accums for no-act[Transform] handle 1-node graphs correctly in SortGraph[Util] catch duplicate annotations in get_by_name[Test] more tolerance in rtlsim throughput testMerge pull request #206 from quetric/feature/acc_thr_bitwidth[Transform] introduce and use MinimizeAccumulatorWidth transform[Util] introduce calculate_matvec_accumulator_range[DataType] add finer-granularity integer types and (u)int64Merge branch 'feature/acc_thr_bitwidth' of https://github.com/quetric/finn into quetric-feature/acc_thr_bitwidthMerge pull request #214 from Xilinx/feature/zcu102Merge branch 'dev' into feature/zcu102[Docs] update getting_started.rst[Test] remove/don't generate tmp files in main folder[Test] fix quicktest.sh main setting[ConvertToHLS] add missing importMerge remote-tracking branch 'origin/dev' into optimize_streamerMerge pull request #201 from Xilinx/feature/depthwise_convolution[Test] fix exp cycle readout in test_convert_to_hls_conv_layer[Test] sim_cycles -> cycles_rtlsimImplemented explicit solution for DEPTH=1 corner-case