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Created with Raphaël 2.2.011Aug1076543131Jul29282724222120171411109876532129Jun2827262524232221191817151412111098543228May27262524222120[Analysis] use node.name as returned dict key, comment on unique names[Pool] add parantheses around exp cycles calc[FMPadding] add parantheses around exp cycles calcMerge branch 'feature/expected_cycles_per_layer' of https://github.com/Xilinx/finn into feature/expected_cycles_per_layer[HLSCustomOp] fix exp cycles for AccPool, band-aid failing test[Test] fix FIFO tests[Analysis] update comment in exp_cycles_per_layerMerge branch 'dev' into feature/expected_cycles_per_layerMerge pull request #199 from quetric/feature_custom_zynq_shell[Driver] fix wait condition for zynq-iodma[Test] don't use debug mode for ZynqBuild end2end testsMerge pull request #208 from HenniOVP/feature/issue_205[Util] Python style compliance[Transform] minor assertion fixes in InsertFIFO and InsertIODMA[Test] add more ZynqBuild tests for tfc-w2a2 and cnv-w1a1Cleaned up core xml, set all support levels to ProductionFixed address range of readmemh in rtl streamer[ZYNQ] remove InsertTLastMarker, support stitching w/o TLastMarker[Core] support renamed tensors for SDP output[Driver] make i/o folded shape dependent on platform[DMA] fix IODMA num outputs[Test] add own test for zynqbuild for now[ZYNQ] add debug/chipscope option[Core] handle renamed inputs to StreamingDataflowPartition correctly[ResUtil] improve nested SDP reporting[ResUtil] handle SDPs with some recursion[Core] only pass relevant inputs to SDP[ZYNQ] generate xml reportUpdated streamer data and depthFixed template for synthesisModified RTL streamer and its instantiation template, removing need for Q_srl in decoupled modeFixes Xilinx/finn#205[Test] Add test for exp cycles to VVAU node test[CustomOp] Add get_exp_cycles for VVAU and threshold pragmasMerge branch 'feature/expected_cycles_per_layer' into feature/depthwise_convolutionMerge branch 'dev' into feature/depthwise_convolution[Deploy] add platform attribute, respect in remote_exec[Driver] changes for zynq-iodma[Test] fixes to zynqbuild test[Vitis] update args for v++ with optimize and report