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Created with Raphaël 2.2.030Apr2928272624232221201917161514987632131Mar30272625242322212019181312111096543228Feb2726252423212019181716141312[Test] run pre-commit hooks for TopK test, cleanup a few thingsMerge branch 'feature/insert_topk' of https://github.com/quetric/finn into quetric-feature/insert_topkSwitched to tensor intializer instead of constant nodeMerge branch 'feature/pynqz1_slim_shell' into feature/throughput_test[Docker] update PYNQ-HelloWorld to get u96 fixesAdded test with 3 values of k[Docker] update PYNQ-HelloWorld to get slim shell data width fix[Test] respect idt for ipstitch on-PYNQ testsVarious fixes. Verified for one scenarioMerge feature/pynqz1_slim_shell into feature/throughput_testMerge feature/streaming_fifo into feature/throughput_test[Notebook] Add FIFO insertion in end2end notebookDraft code for transformation to insert a top-k node at the output of the graph[Transformation] Update FIFO insertion so the depth is set by the node attributes from the surrounding nodes[HLSCustomOp] Change default depth for FIFO related node attributes to 2[Docker] update PYNQ-HelloWorld to make DWCs optional for PYNQ-Z1[Test] fix ipstitch rtlsim to account for AXI lite interface[PYNQ] metadata_prop is always string, cast port arg accordingly[Test] Set in and out fifo depth node attributes for every fpgadataflow node in tfc w1a1[HLSCustomOp] Move inFIFOdepth and outFIFOdepth noe attributes to HLSCustomOp base class[StreamingFIFO] Fix bug in ip generation - naming of toplevel verilog file[Fclk] set default frequency to 100 MHz throughout the project[Test] remove double setting in test tfc_w1a1_fold_and_tlastmarker[PYNQ, IPStitch] introduce fclk as explicit parameter[Docker] update PYNQ-HelloWorld to get slim PYNQ-Z1 shellMerge branch 'dev' into feature/streaming_fifo[Transformation] Integrate util function into prepare rtlsim trafoMerge dev into feature/util_fct_is_fpgadataflow_nodeMerge branch 'feature/throughput_test' into feature/pynqz1_slim_shellMerge branch 'feature/decoupled_ram_style' into dev[Test] specify ram_style for 2 layers in end2end_tfc_w1a1[StreamingFC] rename decoupled_ram_style -> ram_style[StreamingFC] add quote marks to decoupled ram_style arg[StreamingFC] enable decoupled_mem_mode attribute setting[StreamingFC] add quote marks to decoupled ram_style arg[StreamingFC] enable decoupled_mem_mode attribute setting[Core] specify build_dir for pyverilator to keep files[Core] specify build_dir for pyverilator to keep files[StreamingFIFO] Change functions to fit new rtlsim flowMerge branch 'dev' into feature/cnv_w1a1_decoupled