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Created with Raphaël 2.2.013May121187654130Apr2928272624232221201917161514987632131Mar30272625242322212019181312111096543228Feb2726[Deps] add versions for onnx, onnxruntime and npy[Deps] add versions for onnx, onnxruntime and npy[Deps] update Brevitas[Transform] bugfix in MoveReshape, rename to RemoveCNVtoFCFlatten[Deps] update Brevitas to get bipolar threshold export fix[Transform] check attrs in ConvertBipolarMatMulToXnorPopcount[Deps] switch to BNN-PYNQ examples packaged in Brevitas[Infra] remove old-style deps from .gitignore[Deps] don't clone brevitas_cnv_lfc[Deps] update Brevitas to latest finn_onnx_export_dev, pip install[Transformation] Remove warning about clock period in prepare ip transformation[Test] Change clock period back to 10 ns for tfc w1a1[Test] Update other tests that use CreateStitchedIP transformation to use clock period as argument[Test] Change input argument to clock period for make_pynq_proj and create_stitched_ip transformation[Transformation] Add warning if chosen clock period could lead to failure due to clock divider constraints[Transformation] Change input argument from frequency in MHz to clock period in nsMerge branch 'dev' into feature/adjusting_clk_frequency[Test] remove generated .onnx files[Core] check topological sorting before executionMerge pull request #71 from Xilinx/feature/check_topological_order[Analysis] rename to nodes_topologically_sortedMerge branch 'dev' into feature/check_topological_orderMerge pull request #87 from Xilinx/feature/graph_order_util_fct[Deps] update PyVerilator to get Lucian's multifile fix[Transformation and Test] Add option to adjust clock frequency in ipstitch and when making the pynq project get fclk from the metadata properties. Change tfc w1a1 test to test new feature[Blog] small fixes to v0.3b release blog post[Blog] small fixes to v0.3b release blog postMerge branch 'staging/v0.3b' for FINN v0.3b releaseMerge branch 'dev' for FINN v0.3b releaseMerge branch 'staging/v0.3b' of https://github.com/Xilinx/finn into staging/v0.3b[Sphinx-Documentation] Add section about throughput test[README] Update for v0.3b releaseMerge branch 'staging/v0.3b' of https://github.com/Xilinx/finn into staging/v0.3b[rtlsim] don't produce leftover out.npy file during rtlsim[Test] don't save intermediate onnx models in streamline_cnv[Blog] blog post for v0.3b release[Sphinx-Documentation] Update chapter about functional verification[Sphinx-Documentation] Refer from network preparation to new section about mem mode[Sphinx-Documentation] Update chapter about getting started[Sphinx Documentation] Update tutorials chapter