Skip to content
Snippets Groups Projects
Select Git revision
  • accl default
  • adegendt/accl_clone
  • dev
  • full_accl_support
  • georg/accl-build
  • georg/accl-complete
  • georg/accl-finn
  • georg/end2end
  • main protected
9 results
You can move around the graph by using the arrow keys.
Created with Raphaël 2.2.020Feb181613107531Jan262523181716151413129876543228Dec262019131242130Nov29282726242221201710987631Oct30282625242320181714131211109654222Sep18231Aug29282524231798432131Jul2827262521191817121110765429Jun2827262321151413129875130May29262524231716151211954328Apr26252421191811754324Mar231615141310976432128Feb272423222120161514131098732131JanMerge branch 'georg/accl-build' into full_accl_supportfull_accl_supportfull_accl_supportMerge branch 'georg/accl-finn' into full_accl_supportFix accl utilsgeorg/accl-buildgeorg/accl-buildRemove wait for ackgeorg/accl-finngeorg/accl-finnMerge branch 'georg/accl-finn' into full_accl_supportRemove wait for ackRevert ifMerge branch 'full_accl_support' of github.com:fpgasystems/finn into full_accl_supportFix interface accl inMerge branch 'georg/accl-finn' into full_accl_supportFix ap_ctrlFixes to make new version workMerge remote-tracking branch 'origin/georg/end2end' into full_accl_supportDisable ACCL modeFix Coyote upper limitFix standalone modeFix assertion for weight updateCleanupAdd ACCL modeTest fix weight indexAdd ACCL supportFix commentsPrevent creation of interconnect if only one axiliteFix chaining interconnectsAdd address mapAdd HLS bridgeGenerate width convertersUse wrapper fileFix base address for inner interconnectsMake max amount of output parametrizableFix axilite addr widthSupport for chaining interconnectsCleanupRemove connect multipleAdd support for coyote shell[Tests] Remove saving of waveform for dwc test[DWC] Add additional sv file to list of files to copyExtended AXI-lite data bus to next full byte boundary.[Transformation] Use RTL DWC by default[Test] Extend dwc testing to test rtl variant of node