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Created with Raphaël 2.2.013Jan129876543228Dec262019131242130Nov29282726242221201710987631Oct30282625242320181714131211109654222Sep18231Aug29282524231798432131Jul2827262521191817121110765429Jun2827262321151413129875130May29262524231716151211954328Apr26252421191811754324Mar231615141310976432128Feb272423222120161514131098732131Jan3029272624222018171613121110965430Dec2919131286Fix assertion for weight updateMerge pull request #949 from Xilinx/fix/end2end_testCleanupAdd ACCL modeTest fix weight indexAdd ACCL supportFix comments[Tests] Fix end2end cybsec_mlp test[Issue template] Change link to get in touch with communityFreerunning kerneladegendt/accl_c…adegendt/accl_cloneMerge pull request #922 from fpjentzsch/feature/swg_reorderingFix start_callMove start_callacclacclPrevent creation of interconnect if only one axiliteFix chaining interconnectsAdd address mapAdd HLS bridgeParallel buildsFix interface nameAdd global prepare accl stepMerge pull request #835 from hleblevec/feature/pixelpadding[RTL SWG] Use sliced vector assignment to avoid Verilator limitation[Deconv] Update test and add comments to transformation[PixelPadding] Add batchsize for expected cycles calcMerge pull request #945 from Xilinx/fix/rtd[Docs] Separate docs requirements in docs folder[Docs] Add sphinx theme to requirements[Docs] Update syntax in rtd config file[Docs] Update readthedocs config file[Tests] Refactoring of deconv testMerge pull request #942 from timkpaine/patch-1[pixelpad] Omit redundant code and reduce test cases[Tests] Change assertion to pytest skip in brevitas export test[Tests] Fix copyright header in test caseMerge upstream dev and resolve merge conflictGenerate width convertersUse wrapper fileFix base address for inner interconnectsMake max amount of output parametrizableFix axilite addr width