Skip to content
Snippets Groups Projects
Select Git revision
  • accl default
  • adegendt/accl_clone
  • dev
  • full_accl_support
  • georg/accl-build
  • georg/accl-complete
  • georg/accl-finn
  • georg/end2end
  • main protected
9 results
You can move around the graph by using the arrow keys.
Created with Raphaël 2.2.029Dec1913128652125Nov171613108732131Oct2726242119171614131211107654329Sep28272623222019161514987631Aug3029262524221918151211109843129Jul282726252221201918151413121198765430Jun292827242322212017151312109872131May30252423201817161312111098654328Apr2120730Mar2825242322151411842124Feb22Merge pull request #722 from Xilinx/hotfix/ipstitch_test[Tests] Fix ipstitch test for VitisBuild[HLSCustomOp] single-source + prep util fxns for node-by-node rtlsim[Util] refactor verilator prep into two functionsMerge pull request #719 from Xilinx/hotfix/end2end_tests[Test] cover both python and cpp mode for largefifo_rtlsim[Util] remove redundant code from pyverilator utils[Tests] Add missing marker and clean up topk test[Tests] Fix typo in ext_weights file and set verbose to trueMerge branch 'dev' into feature/cppverilator-fifo-rtlsim[VitisBuild] Reverse check for node name in ipgen and add prefix for node names in vitis build[tests] set clk period higher for bnn end2end testsMerge pull request #718 from i-colbert/feature/accumulator_widthUpdate vectorvectoractivation.py[Test] fix test_split_large_fifos, include pow2 behavior[FIFO] cleaner impl of get_fifo_split_configs[tests] Mark cybsec board tests as xfail[tests] Mark ext_weights board tests as xfail[FIFO] better documentation for SplitLargeFIFOs, FIFO in caps[Build] move FIFO splitting past final json folding config file gen[FIFO] support FIFO splitting for pow2 size optimizationsMerge branch 'dev' into hleblevec-feature/split_large_fifosMerge pull request #717 from i-colbert/feature/accumulator_widthUpdating qonnx URL and commitUpdating VVAU LUT estimationUpdating MVAU LUT estimationMerge pull request #716 from Xilinx/hotfix/lint_flake8[pre-commit] Reverse update of flake8 rev[GA] Fix python version in lintin GA[pre-commit] Update rev version for flake8[pre-commit] Specify python for flake8[pre-commit] Update flake8 link[RTL SWG] Rework parallel-output implementation styleMake SIMD support independent from PEMerge pull request #712 from Xilinx/fix/attribute_renaming[notebooks]: ensure that the new (renamed) attribute is addressed correctly[fix-comments]: in/outFIFODepth renamed to in/outFIFODepths[FIFO] bugfixes+improvements in verilator fifosim template[FIFO] improve C++ FIFO sizing template[FIFO] also generate compilation script for C++ FIFO sizing
Loading