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Created with Raphaël 2.2.021Apr201918151412109826Mar25242317543226Feb242322181211108764131Jan29262120171517Dec161413983124Nov231996530Oct282726222120191514131211109876529Sep27262524232120181716151412111095432131Aug30282725242321201918171312111076543131Jul2928272422212017141110987653[Docs] update publickey auth changes[Test] rsync mnist dataset into target for extw end2end test[Infra] remove config.bak, leave up to user[Infra] add default config under ssh_keysApplying memory bank and SLR floorplanning constraints; also added better defaults for memory bank[Test] add board access test using public key[HLSCustomOp] move StreamingDataflowPartition to fpgadataflow opsMerge branch 'dev' into feature/vitis_hls[Driver] throughput_test : fix units + use fast mode if possibleMerge pull request #238 from quetric/feature/ext_weights_refactor[Test] minor fix for end2end extw test if dir exists[InsertIODMA] refactoring: use existing util functions[Test] mark extw end2end tests with vivado and slow[Refactor] make varname more explanatory in InsertDWC[Driver] clear ext weights in loader function[Driver] update comment for load_external_weights[Driver] remove warning about Zynq for ext weights[Test] make 2 layers external for end2end extw test[Test] flesh out ext weights test[Build] do driver creation to later to work with new assumptions[Driver] fix&enable extw on Zynq, add benchmark[Test] introduce new test for external weights[Test] add license header to end2end cybsec mlp testMake linking optional[Test] remove extw end2end test from bnn-pynq, will do differently[HLSCustomOp] comment new get_verilog_top_module_intf_names style[HLSCustomOp] fix Thresholding op to use new interface convention[Refactor] use is_fpgadataflow_node in CreateStitchedIPMerge branch 'feature/ext_weights_refactor' of https://github.com/quetric/finn into quetric-feature/ext_weights_refactorMerge pull request #306 from Xilinx/feature/end2end_test_cybsec_mlp[Test] skip run_on_hw for end2end cybsec when appropriate[Test] end2end test for UNSW-NB15 MLP[Data] add test data for end2end UNSW-NB15 MLP[Driver] use compatible data for throughput testingMerge pull request #301 from fpjentzsch/feature/fix_driver_paddingMerge pull request #305 from Xilinx/feature/tutorial_march21Driver gen: extract folded i/o shapes from IODMA consumer/producerMerge pull request #300 from pete-lennart/notebook_update[Notebook] update cybsec-3 notebook w/ typo fixes[Notebook] rename notebook 2 + fixes from Jakoba + improvements