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Created with Raphaël 2.2.022Sep2019161514987631Aug3029262524221918151211109843129Jul282726252221201918151413121198765430Jun292827242322212017151312109872131May30252423201817161312111098654328Apr2120730Mar2825242322151411842124Feb222019181716151110983131Jan2725211322Dec211716151362130Nov2927262423201615131211108543229Oct28272221201918[Refactor] add optional ind=0 argument to HLSCustomOp stream properties[Refactor] typo fix in DeriveFIFOSizes[Refactor] remove remaining outFIFODepth refs[Refactor] deprecate singuler in/outFIFODepth: in/outFIFODepths onlyWorking initial implementationMerge branch 'feature/rtlsim-vivado-ip' into feature/new-fifo-sizing-residualMerge branch 'feature/vitisbuild' of https://github.com/Xilinx/finn into feature/vitisbuildMerge branch 'dev' into feature/vitisbuildMerge pull request #664 from hleblevec/feature/vitisbuild[InsertDWC] use impl_style=vivado if widths not divisibleMerge branch 'feature/rtlsim-vivado-ip' of github.com:Xilinx/finn into feature/rtlsim-vivado-ip[FIFO] instead of fixed-depth large FIFO in sim, use tensor size[FIFO] instead of fixed-depth large FIFO in sim, use tensor size[FIFO] use hw maxcount monitoring in InsertAndSetFIFODepths[FIFO] add hw maxcount tracking to rtl FIFOs with opt attributeMerge branch 'feature/lookup_bounds' into feature/rtlsim-vivado-ip[Deps] update QONNXMerge branch 'dev' into feature/rtlsim-vivado-ipAddress reviewer commentsfix name in fetch repos and capitalize kv260 in templatesupdate fetch-repos.shMerge pull request #656 from Xilinx/deps/update-qonnx-versionChanges to make[Test] batch-4 inputs and result checking for test_build_dataflow[Build] keep different vcd's from batch inputs[Util] set property on SDP nodes to get full context[Build] support batched verification i/o, one at a timeLint fixMove parallel impl. to different branch, cleanup[pre-commit] Run pre-commit on lookup layer fileRebalanced lookup implementation code to go mostly into header file.Match requested II with achievable one.Maintain static OOB count internally requiring explicit acknowledging reset.Initial QONNX ingestion notebookRemove cell executionRename brevitas_network_import notebook and add intro noteInitial VVAU SIMD supportUpdate basic.pyZynqBuild: use AXI port width from part map[FIFO] move characterization into HLSCustomOp member fxns