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Created with Raphaël 2.2.028Sep272623222019161514987631Aug3029262524221918151211109843129Jul282726252221201918151413121198765430Jun292827242322212017151312109872131May30252423201817161312111098654328Apr2120730Mar2825242322151411842124Feb222019181716151110983131Jan2725211322Dec211716151362130Nov2927262423201615131211108543229OctMerge branch 'feature/rtlsim-vivado-ip' into feature/cppverilator-fifo-rtlsimMerge branch 'feature/rtlsim-vivado-ip' into feature/new-fifo-sizing[Test] parametrize FIFO sizing test for method[FIFO] add new build option to enable C++-based FIFO sizing[FIFO] add new verilator_fifosim util function to call C++ rtlsim[FIFO] C++ template for faster rtlsim with verilator[FIFO] SystemVerilog -> Verilog fix in Q_srl.vMerge pull request #649 from Xilinx/feature/decoupled-vvauMerge pull request #631 from hleblevec/feature/make_scale_resize_nhwc[Pre-commit] Run pre-commit on changed files[customOp] Temp. reverse changes to checksum axilite interface name[FIFO] SystemVerilog -> Verilog fix in Q_srl.vremove unnecessary comments[Deps] Update finn-hlslib commit & fix typoMerge branch 'Xilinx:dev' into devMerge pull request #1 from patrickgeel/mainMerge pull request #691 from Xilinx/feature/axi_infoMerge branch 'main' into devMerge pull request #690 from Xilinx/dependabot/pip/protobuf-3.20.2Bump protobuf from 3.20.1 to 3.20.2Merge dev into feature/decoupled-vvauMerge pull request #648 from Xilinx/feature/streaming_eltwise[MakeScaleResizeNHWC] Update on test script to correct errors. Now also verifying that the transform actually happened rather than just fonctionnality[customOp] Fix typo in eltwise customOpMerge branch 'dev' into feature/swgg_dynamicAdd dynamic mode switchMerge branch 'dev' into feature/streaming_eltwiseMerge remote-tracking branch 'origin/dev' into feature/make_scale_resize_nhwcMerge pull request #677 from fpjentzsch/feature/fix_iodma_widthMerge pull request #607 from fpjentzsch/feature/swgg[CustomOp] Add comments to convinputgen rtl[Style] Minor style fixes to added components[FIFO] fix MVAU characterization tests[Refactor] fix fifo depths property for concat layers at conversion time[Refactor] add missing ind param to Checksum HLSCustomOp[FIFO] simplifying idt retrival after refactor[Refactor] add optional ind=0 argument to HLSCustomOp stream properties[Refactor] typo fix in DeriveFIFOSizes[Refactor] remove remaining outFIFODepth refs[Refactor] deprecate singuler in/outFIFODepth: in/outFIFODepths only