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Created with Raphaël 2.2.029Aug262524221918151211109843129Jul282726252221201918151413121198765430Jun292827242322212017151312109872131May30252423201817161312111098654328Apr2120730Mar2825242322151411842124Feb222019181716151110983131Jan2725211322Dec211716151362130Nov2927262423201615131211108543229Oct2827222120191815141312[Test] baseline for residual FIFO sizing test[FIFO] typo fix for residual experimentMerge pull request #675 from azizb-xlnx/bugfix/azizb/vvau_wstrm_width[FIFO] try sizing bypass FIFOs with a new approach[Test] add residual FIFO sizing testcase, path needs fixVVAU: add weightstream width helperMerge branch 'dev' into feature/decoupled-vvauRevert "Merge branch 'feature/rtlsim-vivado-ip' into feature/new-fifo-sizing-residual"[Build] adjust chrc FIFO sizing for new InsertFIFO behavior[InsertFIFO] change default value of max_qsrl_depth to NoneMerge branch 'feature/rtlsim-vivado-ip' into feature/new-fifo-sizing-residualMerge branch 'dev' into feature/new-fifo-sizing-residual[rtlsim] add custom variant of axis_infrastructure.vh[Build] add option (enabled) to keep impl_style=vivado for rtlsim[rtlsim] experimental support for impl_style=vivado FIFO and DWC sim[Deps] update pyverilator and verilator[Deps] update pyverilatorMerge branch 'dev' into feature/swggRestructure, basic resource estimation[Build] small fixes to new FIFO sizing integration[Stitch] print failing dir if IP stitch fails[Build] add new option and logic for chrc-based auto FIFO sizing[InsertFIFO] add optional args for max QSRL depth and ram_style[FIFO] round up depth to power-of-2 for impl_style=vivado[FIFO] Speed up DeriveFIFOSizes considerably with numpy[HLSCustomOp] Adding ap_none interface stringMerge pull request #668 from Xilinx/feature/manual-verilator-installMerge pull request #670 from Xilinx/feature/lookup_bounds_irq[IP stitch] make new lookup layer output external[Streamline] Updating the transformation to check if the input is in the expected format.Merge branch 'feature/manual-verilator-install' into feature/streaming_eltwise[Deps] manually clone and install particular verilator version[Eltwise] use struct member fxn to workaround HLS pipeline style bug[Test] generalize fifosizing test to enable more nets[FIFO] handle weight reps correctly for decoupled mode[Test] switch to new DeriveFIFOSizes[FIFO] Add DeriveFIFOSizes as NodeLocalTransformation[Deps] update QONNX[FIFO] allow skipping nodes with existing characteristic[Test] flesh out new FIFO sizing test