Skip to content
Snippets Groups Projects
Select Git revision
  • accl default
  • adegendt/accl_clone
  • dev
  • full_accl_support
  • georg/accl-build
  • georg/accl-complete
  • georg/accl-finn
  • georg/end2end
  • main protected
9 results
You can move around the graph by using the arrow keys.
Created with Raphaël 2.2.023Jan22212017161514109873220Dec191817161312111096543229Nov28272625242221201918161514131211109876543131Oct30292524232221181716[PYNQ] specify produced bitfile as attribute[Docker] add pytest-dependency[PYNQ] place output products in PYNQ proj folder[Notebook] rename and give a rough ordering to the notebooks[PYNQ] include all IP dirs for PYNQ project creation[PYNQ] start adding SynthPYNQProject transform[PYNQ] use correct VLNV name, clk and reset signal names[Test] check for vlnv in stitching test[IPI] add stitched IP VLNV as attribute[Transform] remove PYNQ project during cleanup[Transform] fix attr name, hijack test for PYNQ proj creation[Transform] add a first sketch of MakePYNQProject transform[IPI] Refactor attribute name vivado_proj -> vivado_stitch_proj[PYNQ] add dependency repo for PYNQ shellsMerge branch 'feature/ip_stitching' into devMerge branch 'dev' into feature/ip_stitching[Refactor] use metadata_prop accessors from modelwrapper[Transform] remove IP stitching proj during cleanup[ModelWrapper] add get/set for metadata_prop[Test] flesh out IP stitching test[IPI] export stitched design as IP, run Vivado[IPI] set vivado_proj attribute correctly at top levelUpdate example-networks.md[HLSCustomOp] Fixed bug in control loop count in rtlsimMerge branch 'feature/ip_gen_im2col' into feature/ip_gen_fclayer[Execution - Simulation] Added inner and outer loop count to observe the simulation and introduced new abstract method to determine the number of output values[IPI] add module connections, external pins[Test] sketch a basic IPI stitching test[IPI] minor fixes to generated stitching tcl scriptMerge branch 'feature/ip_gen_fclayer' into feature/ip_stitching[IPI] write generated script for stitchingMerge branch 'dev' into feature/ip_gen_im2col[Execution] Changed interpretation of pyverilator output values (uint2 -> int2)[HLSCustomOp] Deleted obsolete prints[IPI] start sketching the IPI stitching pass[notebook] Fixed some grammar mistakesremove the old/unused codegen prototype[notebook] Added last part of HLSCustomOp verification[IPGenBuilder] Added full path to vivado_hls call[notebook] Added first part of HLSCustomOp verification notebook