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Created with Raphaël 2.2.027Jan2624222018171613121110965430Dec291913128652125Nov171613108732131Oct2726242119171614131211107654329Sep28272623222019161514987631Aug3029262524221918151211109843129Jul282726252221201918151413121198765430Jun292827242322212017151312109872131May302524232018171613[Test] remove FIFO attr==0 condition in end2end_bnn_pynq[SWG] Adjust resource estimates, set_folding[FIFO] make FIFO insertions act more consistently[FIFO] set in/outFIFODepths for FIFO nodes themselves to 0[Test] restrict fifosizing test to tfc topologyMerge pull request #692 from patrickgeel/dev[Test] correctly pass topology for fifo sizing test, set fps differently[Deps] update qonnx to get ints attribute fixMerge remote-tracking branch 'upstream/dev' into feature/swgg_dynamic[Test] extend FIFO sizing test to cnv and premade confMerge pull request #736 from i-colbert/feature/accumulator_widthMerge pull request #704 from hleblevec/feature/split_large_fifos[Transform] Add defaults, docstring and comments to split large fifosMerge remote-tracking branch 'upstream/dev' into feature/split_large_fifos[Tests] Extend split large fifo testcase[pyverilator] Add arguments to cpp verilator simulation[VVAU] update resource estimatesMerge pull request #739 from Xilinx/hotfix/GHA[GHA] Update setup-python in pre-commit gha[Tests] Change copyright header and force python verilator execAdded Ultra96-V2Add Ultra96-V2Merge pull request #737 from Xilinx/hotfix/jenkins[Tests] Add jenkins marker for fifosizing testUpdate basic.pyFixing headers to minimize_weight_bit_width.py[Docs] Fix docstring in SplitLargeFIFOs transform[VVAU] SIMD support for decoupled modeMerge remote-tracking branch 'upstream/dev' into feature/split_large_fifosFixing if-else logic to make more senseCreate minimize_weight_bit_width.pyMerge pull request #724 from Xilinx/hotfix/cppsim[CustomOp] Update ImgDim and numReps in thresholdingMerge branch 'dev' into hotfix/cppsimMerge pull request #735 from Xilinx/hotfix/bp_accumulator_widthMerge remote-tracking branch 'upstream/dev' into dev[MVAU] Update minimize accumulator width for bipolar caseFixing reproducibility issue with FINN_BUILD_DIR[FIFO] use at least 2 samples also for convnets for cppsim fifo insertionMerge pull request #734 from Xilinx/fix/documentation