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Created with Raphaël 2.2.07Nov32131Oct2726242119171614131211107654329Sep28272623222019161514987631Aug3029262524221918151211109843129Jul282726252221201918151413121198765430Jun292827242322212017151312109872131May30252423201817161312111098654328Apr2120730Mar2825242322151411842124Feb222019181716151110983131Jan2725211322Dec21Merge branch 'dev' into feature/vitisbuild[Test] add rectangular cases to dynamic spatial FM size testMerge pull request #709 from Xilinx/fix/end2end_bnn_test[Tests] Remove PrepareRTLSim step from bnn testMerge pull request #707 from Xilinx/fix/noconst_streamingeltwiseMerge pull request #708 from Xilinx/hotfix/absorb_tr_resize[Streamline/Absorb] Reorder insertion/rewire of new trn node[Convert] skip streaming eltwise conversion if static inputsMerge remote-tracking branch 'upstream/dev' into feature/vvau_simdMerge pull request #705 from Xilinx/fix/FIFO[CustomOp] Add dtype functions to StreamingFIFO[SWGG] improve HDL code[set_fifo_depths] Adding a new transformation to split fifos larger than the max allowed depthMerge pull request #702 from Xilinx/hotfix/streamdepth_fc[CustomOp] Delete stream depth pragmas for in/out streams in MVAU and VVAUs[SWGG] incorporate Yaman's changes + small fixesMerge branch 'dev' into feature/swgg_dynamicMerge pull request #700 from Xilinx/hotfix/fifo_extw[Transform] Extend inFIFODepths for extw nodes[Test] use higher PE config for dyn conv tests[Test] extend test_fpgadataflow_conv_dynamic coverage[SWG] generate wren as part of config reg generation[Pad] use contiguous, 4b-aligned config addrs for RTL variant[DynConv] make get_dynamic_config return defaults with None params[SWGG] rename dynamic cfg interface to s_axiliteMerge branch 'dev' into feature/vvau_simd[Pad] typo fix in template[Pad] more changes to RTL inst template for Verilog compatibility[Pad] bring FMPadding_rtl shape/dtype/stream fxn interfaces up to speedMerge branch 'feature/fmpadding_dynamic' into feature/fmpadding_dynamic_integration[Test] remove print/debug statements from dynamic conv test[Pad] bugfix: use dynamic parameters for dynamic config gen[Test] cover cases with padding in dynamic conv tests[Pad] switch top-level template SystemVerilog->Verilog[Test] get dynamic conv test ready for dynamic FMPad[Test] add padding support to conv_dynamic test[Test] add explicit timeout to dynamic conv sizing test[Test] cover FMPadding_rtl as part of tests, compute refernece differently[Pad] bugfixes in FMPadding_rtl config genAdd sanity checking for generics.