Skip to content
Snippets Groups Projects
Select Git revision
  • accl default
  • adegendt/accl_clone
  • dev
  • full_accl_support
  • georg/accl-build
  • georg/accl-complete
  • georg/accl-finn
  • georg/end2end
  • main protected
9 results
You can move around the graph by using the arrow keys.
Created with Raphaël 2.2.015Aug1211109843129Jul282726252221201918151413121198765430Jun292827242322212017151312109872131May30252423201817161312111098654328Apr2120730Mar2825242322151411842124Feb222019181716151110983131Jan2725211322Dec211716151362130Nov2927262423201615131211108543229Oct282722212019181514131211108Merge branch 'feature/manual-verilator-install' into feature/streaming_eltwise[Deps] manually clone and install particular verilator version[Eltwise] use struct member fxn to workaround HLS pipeline style bug[Test] generalize fifosizing test to enable more nets[FIFO] handle weight reps correctly for decoupled mode[Test] switch to new DeriveFIFOSizes[FIFO] Add DeriveFIFOSizes as NodeLocalTransformation[Deps] update QONNX[FIFO] allow skipping nodes with existing characteristic[Test] flesh out new FIFO sizing test[FIFO] support characterizing components with decoupled mode weights[FIFO] also do accumulation as part of DeriveCharacteristic[Test] add first sketch for FIFO sizing end2end test[PrepareIP][HLSSynthIP] Fix on a bug where two IPs could have the same name and not correspond to the same object.Merge branch 'Xilinx:feature/vitisbuild' into feature/vitisbuildAdd IRQ signalling output for input bounds violation (to be externalized).[FIFO] fix boundary condition in DeriveCharacteristic[Prepare_IP] Fix on a bug where two IPs could have the same name and not correspond to the same object.[Eltwise] reflect latest hlslib updates[Test] add copyright header to eltwise[Deps] update finn-hlslib[Test] flesh out FIFO characterizatio test for MVAU[FIFO] bugfix: add reset, extra checks[HLSCustomOp] add missing attribute for characterization period[LookUp layer] Fix typo in pragma insertion[Prepare_IP] Fix on a bug where two IPs could have the same name and not correspond to the same object.[LookUp layer] Change hls implementation of LU external[Deps] update QONNX to latest versionMerge pull request #654 from hleblevec/feature/vitisbuild[Floorplan] Hot fix to correct issues in VitisBuild when using multiple axilite interfaces.[Floorplan] Hot fix to correct issues in VitisBuild when using multiple axilite interfaces.[Floorplan] temporary commit[Floorplan] temporary commitLookup through external memory with input bounds checking.Merge branch 'dev' into feature/streaming_eltwiseMerge pull request #647 from Xilinx/feature/builder_verboseMerge branch 'dev' into feature/builder_verboseMerge pull request #646 from Xilinx/fix/qonnx_quant_conv_bias[Test] add test_fclayer_fifocharacterize[FIFO] bugfix in DeriveCharacteristic