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Created with Raphaël 2.2.02Apr131Mar30272625242322212019181312111096543228Feb2726252423212019181716141312111076543131Jan30292827242322212017161514109[Transformation] Add (re)move reshape node trafo[Test] Add conversion to hls layers to cnv end2end test[Test] Add streamlining for cnv end2end test[Test] Add brevitas export and tidy up for cnv end2end test[Refactoring] Split get_stream_width() to in and out stream width functionMerge branch 'feature/datawidthconverter' into dev[Test] Add test for dwc insert trafo to end2end tfc w1a1 test[Transformation] Add control that consumer is not empty in dwc insert trafoMerge branch 'dev' into feature/datawidthconverter[StreamingDWC] Fix bug in npysim related functions[Transformation] Change insertion for dwc nodes to guarantee it is at the right position[Test] use decoupled mem_mode for end2end TFC testsMerge branch 'feature/fc_ip_pack_decoupled_mem' into dev[Transform] add a mem_mode option to InferStreamingFC fxns[Test] grow matrix size and large int dtype for StreamingFC test[StreamingFC] rewrite the .dat generation logic for wt streamers[Util] add prefix option to pack_innermost_dim_as_hex_str[Transformation] Add transformation to add dwc nodes in the appropriate place[StreamingFC] use double weight streamer FIFOs[StreamingFC] simplify weight strm FIFO interface[StreamingDWC] Add dummy npysim path with output = input[Test] Add test for streaming dwc[StreamingDWC] Add execute_node() function for dwc[StreamingFC] manually add Verilog FIFO to streaming weights[StreamingFC] "fix" weight FIFO depth pragma, but it won't work[Test] bring back random input to ip stitch test[Registry] add data width converter to registryFixed images settings and typo[Test] debug changes to ip stitch test[StreamingFC] check current mem depth for decoupled[HLSCustomOp] add a first draft of StreamingDataWidthConverter[Test] switch to 2-FC stitching testcase[Test] fix IP stitching tests w/ ReplaceVerilogRelPaths[StreamingFC] set vlnv differently for decoupled ip gen[Transform] handle more cases in ReplaceVerilogRelPaths[IPPack] support more families for IP packing[Transform] use new attributes in IP stitching[HLSCustomOp] add ip_vlnv attribute[Blog] add QuartzNet blog post[Sphinx Documentation] change text in end2end rst file