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Created with Raphaël 2.2.020Dec19131242130Nov29282726242221201710987631Oct30282625242320181714131211109654222Sep18231Aug29282524231798432131Jul2827262521191817121110765429Jun2827262321151413129875130May29262524231716151211954328Apr26252421191811754324Mar231615141310976432128Feb272423222120161514131098732131Jan3029272624222018171613121110965430Dec291913128652125Nov171613108732131Oct27Use ap_ctrl_hsgeorg/accl-comp…georg/accl-complete[Docs] Fix minor typos `run_docker.sh` -> `run-docker.sh`Update to Brevitas commit hash to a version that contains espcn codeAdd notice about simulatorMove command callAdd accl rtl emulationAdd ap_ctrl_none backFix accl rootRun pre-commit hooksRemove partitioningAdd testsRemove changes to create stitched ip from PRUse lower level function for issuing commandFix issues from refactoringUse lower level function for issuing commandLeave out changes to build flow for nowClean up codeThree partitionsAdd interface widthsMerge branch 'accl' of gitlab.ethz.ch:streichg/finn into acclAdd control portMerge pull request #925 from Xilinx/feature/dwc[Tests] Remove saving of waveform for dwc testBlock until there is data on the streamFix bugRemove ap_ctrl_none[DWC] Add additional sv file to list of files to copyExtended AXI-lite data bus to next full byte boundary.Merge pull request #924 from Xilinx/update/export[Tests] Update export to qonnx export[Transformation] Use RTL DWC by default[Test] Extend dwc testing to test rtl variant of nodeFix clock association and polarity of reset.[Transformation] Extend InsertDWC to derive rtl variant when selected[CustomOp] Initial draft of custom op for dwc rtl component[rtllib] Rename clk, rst in dwc module and first draft of verilog wrapperAXI stream data width converter for integer ratios.Apply to 1x1 kernel, simplify logic, fix edge cases[RTL SWG] Support SIMD < C in window-parallel modeMerge pull request #920 from Xilinx/hotfix/floorplanning