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Created with Raphaël 2.2.019Oct1514131211109876529Sep27262524232120181716151412111095432131Aug30282725242321201918171312111076543131Jul29282724222120171411109876532129Jun28272625242322Merge pull request #234 from quetric/feature/writable_weightsFixed numInWords for DWC[Deps] update to latest finn-base, pyverilator utils moved there[Docker] move to Xilix/finn-baseModified DWC instantiation to process all input words in a single call, optimizing throughputFixed vivado-style FIFO/DWC; removed erroneous layout checks[Docker] allow setting host build dir with FINN_HOST_BUILD_DIR[Docs] document flushing requirement after AXI lite read/write[Test] bring back runtime w. read test, same workaround as writes[Util] bugfix for multi_handshake[Build] bugfixes after axi lite name changeSeveral changes pertaining to stitching/building designs with external weights; added test for external weights designs[Test] test runtime writes for weights, now passing[Util] support simultaneous w+aw in axi-lite[Test] introduce test_runtime_weights[Deps] update finn-base to get rtlsim hooks[Build] restrict to single AXI-lite, get interface name from attr[IPI] allow multiple AXI lite interfaces[StreamingFC] expose axilite depending on attribute[Util] handle lowercase verilator signals transparently[Tests] add missing license header to a few tests[StreamingFC] expose AXI lite streamer cfg port to top level[Transform] more flexible AXI lite name handling for renamingMerge branch 'feature/writable_weights' of https://github.com/quetric/finn into quetric-feature/writable_weightsFixed signal assignmentFix for MEM_WIDTH==32Merge branch 'feature/writable_weights' of https://github.com/quetric/finn into quetric-feature/writable_weightsSome documentation for the streamer address mapAdded missing IP fileMerge branch 'feature/writable_weights' of https://github.com/quetric/finn into quetric-feature/writable_weightsMerge pull request #237 from Xilinx/feature/pyverilator_axilite[Transform] use pyverilator utils from new util pkg[Test] add test_pyverilator_axilite[Resource] add example adder verilog generated by HLS[Util] add pyverilator utils for AXI lite accessAdded AXILite interface for writing weights; tested in behavioural sim with 1 streamMerge pull request #232 from quetric/feature/autosize_fifos[Test] remove manual FIFO insertion from end2end tests[Test] check outputs from fifo depth setting in end2end test[Deps] update finn-base