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Created with Raphaël 2.2.015Sep1412111095432131Aug30282725242321201918171312111076543131Jul29282724222120171411109876532129Jun282726252423222119181715141211109[Test] make end2end rtlsim top-1 measurement optional on env.var.[Test] no rtlsim tests for Alveo in end2end, redundant[Test] add MNIST top-1 accuracy measurement using stitched rtlsim[Transform] remove default clk_ns from CreateStitchedIPMerge branch 'dev' of https://github.com/Xilinx/finn into feature/end2end_fullnet[Test] skip Alveo end2end tests if no Vitis[Deps] update BrevitasMerge branch 'dev' of https://github.com/Xilinx/finn into feature/end2end_fullnet[Test] add input quantizer parallelism to end2end tests[Test] pass kind=zynq/alveo to more end2end tests[Test] deal with CNV ToTensor as preproc[Test] end2end bnn-pynq test bugfix[Test] allow returning top-k from get_golden_io_pair[Util] add get_topk[Test] add preproc + TopK postproc to BNN-PYNQ end2end tests[Transform] support Div in MoveScalarLinearPastInvariants[DataLayout] handle Squeeze/Unsqueeze for InferDataLayouts[Transform] AbsorbMulIntoTopK -> AbsorbMulAddIntoTopKMerge pull request #224 from Xilinx/feature/cleanup_end2end_and_build[Util] do test checkpoint load/skip differently[Test] change k settings for test_topk_insert[Test] fix test streamline fc for new FC nets[Refactor] remove explicit calls to DoubleToSingleFloat[Core] execute DoubleToSingleFloat prior to transforms[Transformation] comment + check empty name in GiveReadableTensorNames[Test] fix debug test w Double2SingleFloat, higher atol[Deps] update Brevitas[Docs] add missing hw build img[Docs] update docs to reflect new hw build system[Refactor] ReplaceVerilogRelPaths called automatically[Notebook] all tfc notebooks now working[Transform] always call ReplaceVerilogRelPaths before PrepareRTLSim[Test] try both decoupled and const mem_mode in stitch test[StreamingFC] bring back IPI codegen for mem_mode=const -- ouchie[Refactor] remove references to old "zynq" platform[PYNQ, Test] remove old PYNQ build method and tests for it[Deps] remove PYNQ-HelloWorld[Notebook] update end2end notebooks to use ZynqBuild[Test] add rtlsim throughput test to end2end[Test] add hw throughput test to end2end test