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Created with Raphaël 2.2.06May54130Apr2928272624232221201917161514987632131Mar30272625242322212019181312111096543228Feb27262524232120Merge pull request #91 from Xilinx/feature/throughput_testMerge branch 'staging/v0.3b' of https://github.com/Xilinx/finn into staging/v0.3b[Test] correct value range for CIFAR-10 data, check class outputMerge branch 'staging/v0.3b' of https://github.com/Xilinx/finn into staging/v0.3b[Trafo - templates] Restructure and add comments to driver.py template[Transformation] Change line to write packed shape for driver.py template[Core] Change ssh command in remote_exec to setting all input arguments for driver.py[Infra] remove coverage from pytest[Notebook] Update Internals Jupyter notebooks[Trafo - templates] Restructure driver.py and add more comments[Trafo - templates] Restructure driver.py with more commands in init function and default arguments[Core] Change ssh driver.py commands to fit new argument style[Analysis] Use new function name to find successors for analysis pass to check topological sortMerge branch 'feature/graph_order_util_fct' into feature/check_topological_order[Test] Change function names of graph order functions in unit test[ModelWrapper] Rename graph order functionsMerge branch 'dev' into feature/graph_order_util_fctMerge branch 'feature/cnv_w1a1_decoupled' into dev[PYNQ] take final layer folding into account for itersPerSample[FIFO] only insert depth > 2 FIFOs[FIFO] Ignore (1,) dims when doing FIFO insertion[HLSMaxPool] add dummy time mux dimension to StreamingMaxPool[Test] add FIFO insertion to cnv-w1a1 end2endMerge branch 'dev' into feature/cnv_w1a1_decoupledMerge branch 'feature/rtlsim_trace_depth' into dev[Test] remove tracing from end2end tests[rtlsim] Pass trace depth when building pyverilator[Util] add helper fxn to get rtlsim trace depth setting[Deps] update PyVerilator to get trace depth control[Test] disable traces in cnv_w1a1 end2end test[Deps] update hlslib to get pragma-free SWG[SWG] add ram_style attribute for SWG and produce resource directive[HLSCustomOp] allow ops to produce extra HLS directivesMerge branch 'dev' into feature/cnv_w1a1_decoupledMerge branch 'feature/streaming_fifo' into devMerge pull request #85 from Xilinx/feature/streaming_fifoMerge branch 'dev' of https://github.com/Xilinx/finn into feature/streaming_fifo[HLSCustomOp] minor comments to new fxns[Test] Add more networks to test topological sort analysis pass[Analysis] Add condition if successor list is None to check topological order analysis pass