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Created with Raphaël 2.2.09Feb8732131Jan3029272624222018171613121110965430Dec291913128652125Nov171613108732131Oct2726242119171614131211107654329Sep28272623222019161514987631Aug3029262524221918151211109843129Jul282726252221201918151413121198765430Jun29282724232221201715131210987[Docs] Update internals section[hotfix] mark build dataflow test as xfail[Docs] Update code links in command line section[Docs] Add additional packages to docs setup[Docs] Change pyverilator branch to master in setup.cfg[Docs] Fix typo in setup.cfg[Docs] Add pyverilator dependency for automatically build docs[Docs] Fix automatically generated code for FINN builder[Docs] Update end2end flow description[Tutorial] Update README in tutorialMerge branch 'dev' into fix/documentationMerge pull request #756 from Xilinx/fix/notebooksMerge branch 'dev' into fix/notebooks[Notebooks] Update end2end notebooks[Notebooks] Update text in advanced and basics nbs[Notebooks] Change board execution section in cnv notebook[Notebooks] Change board execution section in tfc notebook[Notebooks] General updates of Jupyter notebooksMerge pull request #755 from Xilinx/hotfix/bump-isort-5.12.0[Lint] bump isort version to 5.12.0Fix top module setting in CreateStitchedIPMerge branch 'dev' into feature/test_fifosizing_cnvMerge branch 'dev' into fix/documentation[Docs] Update python version in rtd yaml[Docs] Remove finn-base dependency for docs buildMerge pull request #752 from Xilinx/hotfix/rtlsim_performance[Builder] Move extraction of rtlsim depthMerge pull request #746 from mmrahorovic/fix/onnx-upgrade[Docs] Update links for getting started[DWC] always use hls mode during insertion for better compat[deps]: updated commit hash QONNXMerge remote-tracking branch 'upstream/dev' into fix/onnx-upgradeMerge pull request #749 from Xilinx/fix/firstfifo_vivadoMerge pull request #748 from Xilinx/hotfix/fifo_insertionMerge branch 'dev' into fix/firstfifo_vivado[Test] add cnv testcase as part for FIFO sizing test[Build] calculate stable_throughput metric as part of step_measure_rtlsim_performance[FIFO] use impl_style=hls for first&last FIFOs to avoid glitch[Tests] Ensure that i/o FIFOs are created for dynamic swg tests[Stitch] add warning if first FIFO in graph has impl_style=vivado