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Created with Raphaël 2.2.023Mar22212019181312111096543228Feb2726252423212019181716141312111076543131Jan30292827242322212017161514109873220Dec19181716131211109654[StreamingFC] Change function template of streaming MVAU and make template parameters for decoupled mode equal to embedded (const) modeMerge branch 'dev' into feature/weight_streamers_npysim[StreamingFC] Make decoupled mode template parameters for c++ code generation equal to embedded (const) mode[Test] more progress towards cnv-w1a1 hls conversion[Transform] add MakeMaxPoolNHWC[Transform] add AbsorbTransposeIntoMultiThreshold[Test] start preparing test_convert_to_hls_layers_cnv_w1a1[Test] add NHWC option to MultiThreshold test[CustomOp] add data_layout options to MultiThresholdMerge branch 'feature/cnv_w1a1_streamline' into dev[Transform] add MoveScalarMulPastConv and call in streamlining[Transform] add MoveScalarAddPastConv, use in streamlining[Transform] add ConvertDivToMul transform, call in streamlining[Test] make test_const_folding_shapes more robust to example chgs[Test] make test_modelwrapper more robust to example model changes[Deps] correct branch name for brevitas_cnv_lfc[Test] Add mem_mode "decoupled to rtlsim tests of fclayer"[StreamingFC] Add rtlsim (node-by-node) option for decoupled mode to corresponding functions[Templates - fpgadataflow] Add template for rtlsim[Test] more progress on conv streamlining[Test] simplify and generalize Brevitas CNV export test[Util] make CNV inbits 8 by default[Test] add Brevitas act quant test[Docker] switch to feature branch for examples[Test] call DoubleToSingleFloat for cnv import test[Transform] add DoubleToSingleFloat transformation[Test] Add mem mode as pytest variable for rtlsimMerge branch 'dev' into feature/weight_streamers_rtlsim[StreamingFC] Generation of .dat file into generate_params function[finn-rtllib] Renamed file ramb18.v to ramb18_wf_dualport.v[Util] add other PYNQ boards to pynq_part_map[Streamline] add Absorb1BitMulIntoConv into Streamline[StreamingFC] Save weights array into .dat file and save in verilog folderFix image link in blog postRename 2020_03_11-rn50-released.md to 2020-03-11-rn50-released.mdMerge pull request #59 from quetric/masterBlog post for rn50 releaseAdded illustration for RN50 IPI-based compilation[StreamingFC] Copy rtllib memstream verilog files automatically after ip block is generated for MVAU in decoupled mode[Streamline] add a first v of Absorb1BitMulIntoConv (untested)