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Created with Raphaël 2.2.010Jan965430Dec291913128652125Nov171613108732131Oct2726242119171614131211107654329Sep28272623222019161514987631Aug3029262524221918151211109843129Jul282726252221201918151413121198765430Jun292827242322212017151312109872131May30252423201817161312111098654328Apr2120730Mar28252423[VVAU] Fix BIPOLAR/TERNARY compatibilityMerge pull request #727 from i-colbert/feature/accumulator_widthMerge pull request #730 from Xilinx/hotfix/numpy_int[Util] Change np.int to np.int_Merge pull request #728 from Xilinx/hotfix/numpy_str[Requirements] Fix version for psutil[Docker] add ignore installed for jupyter package[DataPacking] Delete check for np.strAdding check for runtime_writeable_weightsMerge pull request #1 from i-colbert/feature/minimize_weight_bit_widthMerge pull request #726 from Xilinx/fix/requirementsAdding new function attribute to MVAU and VVAU[requirements] Remove future python packageMerge pull request #725 from Xilinx/fix/GHA[GHA] Update quicktest to ubuntu 20.04[GHA] Update docker image testing to ubuntu 20.04Merge branch 'dev' into fix/documentationMerge pull request #694 from Xilinx/feature/cppverilator-fifo-rtlsim[CustomOp] Fix setting of NumReps in Thresholding and N in Eltwise nodeMerge branch 'dev' into feature/cppverilator-fifo-rtlsim[Docs] Update source code rsts for new features[Docs] Fix docstrings in modulesMerge pull request #722 from Xilinx/hotfix/ipstitch_test[Tests] Fix ipstitch test for VitisBuild[HLSCustomOp] single-source + prep util fxns for node-by-node rtlsim[Util] refactor verilator prep into two functionsMerge pull request #719 from Xilinx/hotfix/end2end_tests[Test] cover both python and cpp mode for largefifo_rtlsim[Util] remove redundant code from pyverilator utils[Tests] Add missing marker and clean up topk test[Tests] Fix typo in ext_weights file and set verbose to trueMerge branch 'dev' into feature/cppverilator-fifo-rtlsim[VitisBuild] Reverse check for node name in ipgen and add prefix for node names in vitis build[tests] set clk period higher for bnn end2end testsMerge pull request #718 from i-colbert/feature/accumulator_widthUpdate vectorvectoractivation.py[Test] fix test_split_large_fifos, include pow2 behavior[FIFO] cleaner impl of get_fifo_split_configs[tests] Mark cybsec board tests as xfail[tests] Mark ext_weights board tests as xfail