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Created with Raphaël 2.2.025Aug24221918151211109843129Jul282726252221201918151413121198765430Jun292827242322212017151312109872131May30252423201817161312111098654328Apr2120730Mar2825242322151411842124Feb222019181716151110983131Jan2725211322Dec211716151362130Nov2927262423201615131211108543229Oct282722212019181514131211Restructure, basic resource estimation[Build] small fixes to new FIFO sizing integration[Stitch] print failing dir if IP stitch fails[Build] add new option and logic for chrc-based auto FIFO sizing[InsertFIFO] add optional args for max QSRL depth and ram_style[FIFO] round up depth to power-of-2 for impl_style=vivado[FIFO] Speed up DeriveFIFOSizes considerably with numpy[HLSCustomOp] Adding ap_none interface stringMerge pull request #668 from Xilinx/feature/manual-verilator-installMerge pull request #670 from Xilinx/feature/lookup_bounds_irq[IP stitch] make new lookup layer output external[Streamline] Updating the transformation to check if the input is in the expected format.Merge branch 'feature/manual-verilator-install' into feature/streaming_eltwise[Deps] manually clone and install particular verilator version[Eltwise] use struct member fxn to workaround HLS pipeline style bug[Test] generalize fifosizing test to enable more nets[FIFO] handle weight reps correctly for decoupled mode[Test] switch to new DeriveFIFOSizes[FIFO] Add DeriveFIFOSizes as NodeLocalTransformation[Deps] update QONNX[FIFO] allow skipping nodes with existing characteristic[Test] flesh out new FIFO sizing test[FIFO] support characterizing components with decoupled mode weights[FIFO] also do accumulation as part of DeriveCharacteristic[Test] add first sketch for FIFO sizing end2end test[PrepareIP][HLSSynthIP] Fix on a bug where two IPs could have the same name and not correspond to the same object.Merge branch 'Xilinx:feature/vitisbuild' into feature/vitisbuildAdd IRQ signalling output for input bounds violation (to be externalized).[FIFO] fix boundary condition in DeriveCharacteristic[Prepare_IP] Fix on a bug where two IPs could have the same name and not correspond to the same object.[Eltwise] reflect latest hlslib updates[Test] add copyright header to eltwise[Deps] update finn-hlslib[Test] flesh out FIFO characterizatio test for MVAU[FIFO] bugfix: add reset, extra checks[HLSCustomOp] add missing attribute for characterization period[LookUp layer] Fix typo in pragma insertion[Prepare_IP] Fix on a bug where two IPs could have the same name and not correspond to the same object.[LookUp layer] Change hls implementation of LU external[Deps] update QONNX to latest version