Commits · fe6dca926fa6f1ba1f044cb05a752c586ed3df3a · streichg / Finn · GitLab

Snippets Groups Projects

To receive notifications about scheduled maintenance, please subscribe to the mailing-list gitlab-operations@sympa.ethz.ch. You can subscribe to the mailing-list at https://sympa.ethz.ch

Dec 30, 2022
- [Docs] Fix docstrings in modules · fe6dca92
  auphelia authored 2 years ago
  
  fe6dca92
Dec 08, 2022
- [VitisBuild] Reverse check for node name in ipgen and add prefix for node names in vitis build · 5bfdc0e0
  auphelia authored 2 years ago
  
  5bfdc0e0
Nov 16, 2022
- [fix-comments]: in/outFIFODepth renamed to in/outFIFODepths · ea7518e2
  mmrahorovic authored 2 years ago
  
  ea7518e2
Nov 01, 2022
- [Streamline/Absorb] Reorder insertion/rewire of new trn node · c3083929
  auphelia authored 2 years ago
  
  c3083929
- [Convert] skip streaming eltwise conversion if static inputs · a8343b2d
  Yaman Umuroglu authored 2 years ago
  
  a8343b2d
Oct 27, 2022
- [CustomOp] Add dtype functions to StreamingFIFO · ad6319d5
  auphelia authored 2 years ago
  
  ad6319d5
Oct 24, 2022
- [CustomOp] Delete stream depth pragmas for in/out streams in MVAU and VVAUs · 5d8a0260
  auphelia authored 2 years ago
  
  5d8a0260
Oct 21, 2022
- [Transform] Extend inFIFODepths for extw nodes · c7c15b7c
  auphelia authored 2 years ago
  
  c7c15b7c
Oct 07, 2022
- [EltWise] Change order for node attribute update · a799fe85
  auphelia authored 2 years ago
  
  a799fe85
- [EltWise] Add node attribute for inFIFODepths · 01a62e7f
  auphelia authored 2 years ago
  
  01a62e7f
Oct 06, 2022
- [Refactor] Minor fixes on code · c0dc4af4
  auphelia authored 2 years ago
  
  c0dc4af4
- [CustomOp] Update fmpadding to new hls code · 4c0978e8
  auphelia authored 2 years ago
  
  4c0978e8
Oct 05, 2022
- [CustomOp] Remove overwriting of default FIFO sizes · 72ded22a
  auphelia authored 2 years ago
  
  72ded22a
- [CustomOps] Add missing indices in shape/datatype fcts · 392052b1
  auphelia authored 2 years ago
  
  392052b1
Oct 04, 2022
- [Util] Add comment about usage of axis infrastructure vh · 1ce5af77
  auphelia authored 2 years ago
  
  1ce5af77
- [Stitch] explicitly mark finn_design as top level · acefb525
  Yaman Umuroglu authored 2 years ago
  
  acefb525
Sep 28, 2022
- Revert "Revert "Merge branch 'feature/rtlsim-vivado-ip' into feature/new-fifo-sizing-residual"" · 04217956
  Yaman Umuroglu authored 2 years ago
  
  This reverts commit fc9e880a.
  04217956
Sep 26, 2022
- [customOp] Temp. reverse changes to checksum axilite interface name · 584f0fb5
  auphelia authored 2 years ago
  
  584f0fb5
Sep 23, 2022
- [customOp] Fix typo in eltwise customOp · edf0a91e
  auphelia authored 2 years ago
  
  edf0a91e
- [CustomOp] Add comments to convinputgen rtl · 77f07339
  auphelia authored 2 years ago
  
  77f07339
Sep 22, 2022
- [Style] Minor style fixes to added components · fdb00bb5
  auphelia authored 2 years ago
  
  fdb00bb5
- [Refactor] fix fifo depths property for concat layers at conversion time · 5b1b2ebe
  Yaman Umuroglu authored 2 years ago
  
  5b1b2ebe
- [Refactor] add missing ind param to Checksum HLSCustomOp · 6933d080
  Yaman Umuroglu authored 2 years ago
  
  6933d080
- [FIFO] simplifying idt retrival after refactor · 9375e30d
  Yaman Umuroglu authored 2 years ago
  
  9375e30d
- [Refactor] add optional ind=0 argument to HLSCustomOp stream properties · 3f2d6d97
  Yaman Umuroglu authored 2 years ago
  
  3f2d6d97
- [Refactor] typo fix in DeriveFIFOSizes · 06f9f81a
  Yaman Umuroglu authored 2 years ago
  
  06f9f81a
- [Refactor] remove remaining outFIFODepth refs · ab8fe1e2
  Yaman Umuroglu authored 2 years ago
  
  ab8fe1e2
- [Refactor] deprecate singuler in/outFIFODepth: in/outFIFODepths only · 394d1fa2
  Yaman Umuroglu authored 2 years ago
  
  394d1fa2
Sep 20, 2022
- [InsertDWC] use impl_style=vivado if widths not divisible · d4e91a19
  Yaman Umuroglu authored 2 years ago
  
  d4e91a19
- [FIFO] instead of fixed-depth large FIFO in sim, use tensor size · 6ccc9499
  Yaman Umuroglu authored 2 years ago
  
  6ccc9499
- [FIFO] instead of fixed-depth large FIFO in sim, use tensor size · 20e4613f
  Yaman Umuroglu authored 2 years ago
  
  20e4613f
Sep 19, 2022
- [FIFO] use hw maxcount monitoring in InsertAndSetFIFODepths · 81f010b8
  Yaman Umuroglu authored 2 years ago
  
  81f010b8
- [FIFO] add hw maxcount tracking to rtl FIFOs with opt attribute · e8f7c756
  Yaman Umuroglu authored 2 years ago
  
  e8f7c756
Sep 16, 2022
- Address reviewer comments · 5e0e8989
  Felix Jentzsch authored 2 years ago
  
  5e0e8989
Sep 14, 2022
- [Test] batch-4 inputs and result checking for test_build_dataflow · 10329d79
  Yaman Umuroglu authored 2 years ago
  
  10329d79
- [Build] keep different vcd's from batch inputs · 08134558
  Yaman Umuroglu authored 2 years ago
  
  08134558
- [Util] set property on SDP nodes to get full context · 25499411
  Yaman Umuroglu authored 2 years ago
  
  25499411
- [Build] support batched verification i/o, one at a time · 38d65435
  Yaman Umuroglu authored 2 years ago
  
  38d65435
Sep 09, 2022
- Lint fix · dfb42854
  Felix Jentzsch authored 2 years ago
  
  dfb42854
- Move parallel impl. to different branch, cleanup · 57f9fecd
  Felix Jentzsch authored 2 years ago
  
  57f9fecd