Commits · fa94399d22fc57745f76268ec82ed9b602bfb297 · streichg / Finn · GitLab

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Dec 01, 2021
- [Docker] bring back openssh-client · fa94399d
  Yaman Umuroglu authored 3 years ago
  
  fa94399d
- [Docker] install lsb-core, restructure apt-get install part · d9c6d6f6
  Yaman Umuroglu authored 3 years ago
  
  d9c6d6f6
Nov 30, 2021
- [Vitis] try to fix iface naming for 2021.2 · 8b56f4a5
  Yaman Umuroglu authored 3 years ago
  
  8b56f4a5
- [Vitis] also add std=c++14 for HLS ip synth · 955747f1
  Yaman Umuroglu authored 3 years ago
  
  955747f1
- [Vitis] minor fixes for 2021.1 and Versal Prime parts · 91eaf3b1
  Yaman Umuroglu authored 3 years ago
  
  91eaf3b1
Nov 29, 2021
- [Infra] 2021.2 onwards moves HLS includes, fix via internal env.var · c125afa8
  Yaman Umuroglu authored 3 years ago
  
  c125afa8
Nov 26, 2021
- [Concat] fix stitching for Vitis HLS · 9cfc9b1d
  Yaman Umuroglu authored 3 years ago
  
  9cfc9b1d
- [Deps] update to xdist 2.4.0 to get parallel test proc titles · c1c6b05d
  Yaman Umuroglu authored 3 years ago
  
  c1c6b05d
- [MaxPool] switch to non-_Batch for vitis, no exp cycle checking in test · 7b350d7f
  Yaman Umuroglu authored 3 years ago
  
  7b350d7f
- [HLSCustomOp] fix param mismatches between hlslib and generated code · bf2b6291
  Yaman Umuroglu authored 3 years ago
  
  bf2b6291
- [Deps] update hlslib · c6131f9b
  Yaman Umuroglu authored 3 years ago
  
  c6131f9b
Nov 24, 2021
- Merge branch 'dev' into feature/vitis_hls · dfe7f584
  Yaman Umuroglu authored 3 years ago
  
  dfe7f584
- Merge pull request #451 from Xilinx/feature/pool_flex · 30aa49f3
  Yaman Umuroglu authored 3 years ago
  
  Make Pool_Batch more flexible
  30aa49f3
- [Deps] update hlslib · 7a12c616
  Yaman Umuroglu authored 3 years ago
  
  7a12c616
- [Test] enable 1D tests + restructure convert_to_hls_pool_batch · 63f52f19
  Yaman Umuroglu authored 3 years ago
  
  63f52f19
- [Pool] more steps towards non-square support, square imgs working again · 123892ff
  Yaman Umuroglu authored 3 years ago
  
  123892ff
Nov 23, 2021
- [ConvertToHLS] round of fixes to allow non-square pool, not yet done · 61b349f9
  Yaman Umuroglu authored 3 years ago
  
  61b349f9
- [Test] support creating 1d maxpool in convert_to_hls_pool_batch · b6a5b35e
  Yaman Umuroglu authored 3 years ago
  
  b6a5b35e
- [Pool] change Pool_Batch to use kernel size as list, not scalar · eb2652af
  Yaman Umuroglu authored 3 years ago
  
  eb2652af
- [Pool] adjust kernel param as total k · 18d17bfd
  Yaman Umuroglu authored 3 years ago
  
  18d17bfd
- [Deps] update hlslib · 4b93d77b
  Yaman Umuroglu authored 3 years ago
  
  4b93d77b
Nov 20, 2021
- Merge pull request #443 from Xilinx/feature/concat · 11df4ba2
  Yaman Umuroglu authored 3 years ago
  
  Streaming Concat op support
  11df4ba2
Nov 19, 2021
- [Vitis] don't call layout inference in VitisBuild · fb3a8237
  Yaman Umuroglu authored 3 years ago
  
  fb3a8237
- [Build] better resolution for unspec'd Vitis platform for Alveo · d6ca2e2e
  Yaman Umuroglu authored 3 years ago
  
  d6ca2e2e
Nov 16, 2021
- [Thresholding] switch to single spatial size · ffd894f0
  Yaman Umuroglu authored 3 years ago
  
  ffd894f0
- [Deps] update hlslib · 650b18e5
  Yaman Umuroglu authored 3 years ago
  
  650b18e5
Nov 15, 2021
- Merge branch 'dev' into feature/vitis_hls · c08e2e1a
  Yaman Umuroglu authored 3 years ago
  
  c08e2e1a
- [Hotfix] remove extras=True for tests in setup.cfg · 29d4d790
  Yaman Umuroglu authored 3 years ago
  
  29d4d790
Nov 13, 2021
- [SetFolding] handle ConvolutionInputGenerator1D as well · cc648647
  Yaman Umuroglu authored 3 years ago
  
  cc648647
- [Build] pass large_fifo_mem_style correctly · ae5cb636
  Yaman Umuroglu authored 3 years ago
  
  ae5cb636
- [SWG] no parallel window output with bram/uram ram_style from 1D SWG · 61a293a3
  Yaman Umuroglu authored 3 years ago
  
  61a293a3
Nov 12, 2021
- [Test] add ipstitch+rtlsim test for concat · 067d165b
  Yaman Umuroglu authored 3 years ago
  
  067d165b
- [Deps] update finn-base · db37e945
  Yaman Umuroglu authored 3 years ago
  
  db37e945
- [Infra] don't install extras pkgs during test · 5e7a2ce1
  Yaman Umuroglu authored 3 years ago
  
  5e7a2ce1
- [Concat] make both cppsim and rtl/stitched-ip rtlsim work · 7a5146c4
  Yaman Umuroglu authored 3 years ago
  
  7a5146c4
- [Stitch] gen hierarchical util report if synthesized dcp · 529bc249
  Yaman Umuroglu authored 3 years ago
  
  529bc249
- [Concat] allow indexing get_input_datatype, does nothing though · 14206f6f
  Yaman Umuroglu authored 3 years ago
  
  14206f6f
- [InsertFIFO] fixes when first node has multiple inputs · 8827ab97
  Yaman Umuroglu authored 3 years ago
  
  8827ab97
Nov 10, 2021
- [SWG] updates to ConvolutionInputGenerator1D resource estimates · 1c37c8d7
  Yaman Umuroglu authored 3 years ago
  
  1c37c8d7
- [Stitch] fix ext interface ordering for multi-I/O · c251fbc5
  Yaman Umuroglu authored 3 years ago
  
  c251fbc5