Updated architecture families to all current types, minus the CPLDs

Build and Fclk fixes for Zynq UltraScale+

Fixes & features for multi-output/object detection networks

add warning in CreateStitchedIP

change the resolve_type of interfaces to avoid linking errors for
newer Alveo shells

* config option for saving waveform traces
* cleaner impl for setting rtlsim-friendly FIFO and DWC types

verification: enable returning full-context checkpoints
stitched-IP: enable running synthesis to get DCP