Commits · 9c2a7eeac4618c12c3f0e82ee06afb4b37e6aa2f · streichg / Finn · GitLab

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Feb 20, 2022
- [transform]: support for ceil mode MaxPool · 9c2a7eea
  mmrahorovic authored 3 years ago
  
  9c2a7eea
Feb 18, 2022
- [custom_op]: corrected maxpool in/out stream width and shapes · 7b970fa8
  mmrahorovic authored 3 years ago
  
  7b970fa8
- [convert_hls]: modifications to enable 1D MaxPool layers with PE /... · 69c67c58
  mmrahorovic authored 3 years ago
  
  [convert_hls]: modifications to enable 1D MaxPool layers with PE / non-divisible pool/image dimensions
  69c67c58
Feb 17, 2022
- [custom_op]: PE-parallelism support for 1D MaxPool layers · 6e9a554f
  mmrahorovic authored 3 years ago
  
  6e9a554f
Feb 15, 2022
- [Builder] allow passing rtlsim hook to verification · 57b047a8
  Yaman Umuroglu authored 3 years ago
  
  57b047a8
Feb 10, 2022
- [Lookup] reverse output layout + associated fixes · 40514ced
  Yaman Umuroglu authored 3 years ago
  
  40514ced
Feb 09, 2022
- temp changes · 9bcd945a
  mmrahorovic authored 3 years ago
  
  9bcd945a
Feb 01, 2022
- [Build] don't cast validation i/o data to float32 while loading · 3b10bfe5
  Yaman Umuroglu authored 3 years ago
  
  3b10bfe5
- [QONNX] support Quant -> Gather for quantized embeddings · 53277127
  Yaman Umuroglu authored 3 years ago
  
  53277127
Jan 27, 2022
- [ConvertToHLS] make 1D SWG kernel check more constrained · 2d5d5fd2
  Yaman Umuroglu authored 3 years ago
  
  2d5d5fd2
- [HLSCustomOp] update exp cycles for stride>1 1D DWS SWG · 2bcc816f
  Yaman Umuroglu authored 3 years ago
  
  2bcc816f
- [ConvertToHLS] re-enable 1D SWG DW conv with stride · 5a08858b
  Yaman Umuroglu authored 3 years ago
  
  5a08858b
- [HLSCustomOp] bring back old impl for 1D DWS SWG · d334d482
  Yaman Umuroglu authored 3 years ago
  
  d334d482
Jan 21, 2022
- [custom_op]: support for 1D SWU · 21514001
  mmrahorovic authored 3 years ago
  
  21514001
Dec 17, 2021
- [ChannelwiseOp] promote all dtypes to odt for correct add operation · 6f8040cf
  Yaman Umuroglu authored 3 years ago
  
  6f8040cf
- [Pool] correctly add all headers for codegen · d68d26bd
  Yaman Umuroglu authored 3 years ago
  
  d68d26bd
- [HLSCustomOp] adapt comp:: act types to use new template params · b1820507
  Yaman Umuroglu authored 3 years ago
  
  b1820507
Dec 16, 2021
- [custom_op]: support for 1D SWU and other small modifications · d7a5881b
  mmrahorovic authored 3 years ago
  
  d7a5881b
Dec 15, 2021
- [Pool] add activations.hpp to pool codegen includes · 27fa5582
  Yaman Umuroglu authored 3 years ago
  
  27fa5582
- [ChannelwiseOp] use cmp:: namespace for all channelwise fxns · b324c9b6
  Yaman Umuroglu authored 3 years ago
  
  b324c9b6
Dec 13, 2021
- [FC] bugfix for ext weights fifo insertion (dtype for ind!=0) · 578c8ad2
  Yaman Umuroglu authored 3 years ago
  
  578c8ad2
Nov 30, 2021
- [Vitis] try to fix iface naming for 2021.2 · 8b56f4a5
  Yaman Umuroglu authored 3 years ago
  
  8b56f4a5
- [Vitis] also add std=c++14 for HLS ip synth · 955747f1
  Yaman Umuroglu authored 3 years ago
  
  955747f1
- [Vitis] minor fixes for 2021.1 and Versal Prime parts · 91eaf3b1
  Yaman Umuroglu authored 3 years ago
  
  91eaf3b1
Nov 29, 2021
- [Infra] 2021.2 onwards moves HLS includes, fix via internal env.var · c125afa8
  Yaman Umuroglu authored 3 years ago
  
  c125afa8
Nov 26, 2021
- [Concat] fix stitching for Vitis HLS · 9cfc9b1d
  Yaman Umuroglu authored 3 years ago
  
  9cfc9b1d
- [MaxPool] switch to non-_Batch for vitis, no exp cycle checking in test · 7b350d7f
  Yaman Umuroglu authored 3 years ago
  
  7b350d7f
- [HLSCustomOp] fix param mismatches between hlslib and generated code · bf2b6291
  Yaman Umuroglu authored 3 years ago
  
  bf2b6291
Nov 24, 2021
- [Pool] more steps towards non-square support, square imgs working again · 123892ff
  Yaman Umuroglu authored 3 years ago
  
  123892ff
Nov 23, 2021
- [ConvertToHLS] round of fixes to allow non-square pool, not yet done · 61b349f9
  Yaman Umuroglu authored 3 years ago
  
  61b349f9
- [Pool] change Pool_Batch to use kernel size as list, not scalar · eb2652af
  Yaman Umuroglu authored 3 years ago
  
  eb2652af
- [Pool] adjust kernel param as total k · 18d17bfd
  Yaman Umuroglu authored 3 years ago
  
  18d17bfd
Nov 19, 2021
- [Vitis] don't call layout inference in VitisBuild · fb3a8237
  Yaman Umuroglu authored 3 years ago
  
  fb3a8237
- [Build] better resolution for unspec'd Vitis platform for Alveo · d6ca2e2e
  Yaman Umuroglu authored 3 years ago
  
  d6ca2e2e
Nov 16, 2021
- [Thresholding] switch to single spatial size · ffd894f0
  Yaman Umuroglu authored 3 years ago
  
  ffd894f0
Nov 13, 2021
- [SetFolding] handle ConvolutionInputGenerator1D as well · cc648647
  Yaman Umuroglu authored 3 years ago
  
  cc648647
- [Build] pass large_fifo_mem_style correctly · ae5cb636
  Yaman Umuroglu authored 3 years ago
  
  ae5cb636
- [SWG] no parallel window output with bram/uram ram_style from 1D SWG · 61a293a3
  Yaman Umuroglu authored 3 years ago
  
  61a293a3
Nov 12, 2021
- [Concat] make both cppsim and rtl/stitched-ip rtlsim work · 7a5146c4
  Yaman Umuroglu authored 3 years ago
  
  7a5146c4
- [Stitch] gen hierarchical util report if synthesized dcp · 529bc249
  Yaman Umuroglu authored 3 years ago
  
  529bc249