Commits · 84a6e9b378497b5cb767d64ae228f4a42478219d · streichg / Finn · GitLab

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Jul 14, 2022
- Revert "Merge pull request #637 from Xilinx/dev" · 963fde53
  auphelia authored 2 years ago
  
  This reverts commit fe4a150c, reversing changes made to c98c2211.
  963fde53
Nov 30, 2021
- [Vitis] minor fixes for 2021.1 and Versal Prime parts · 91eaf3b1
  Yaman Umuroglu authored 3 years ago
  
  91eaf3b1
Sep 30, 2021
- Updated achritecture families to all current types, minus the CPLDs · bda18b3d
  john authored 3 years ago
  
  bda18b3d
Dec 17, 2020
- [Release] merge dev into master for v0.5b · 4fee6ffd
  Yaman Umuroglu authored 4 years ago
  
  4fee6ffd
Oct 09, 2020
- Added AXILite interface for writing weights; tested in behavioural sim with 1 stream · ee57c98c
  Lucian Petrica authored 4 years ago
  
  ee57c98c
Sep 17, 2020
- Added all synthesis source files to be used for simulation too · 27863700
  john authored 4 years ago
  
  27863700
Aug 21, 2020
- Updated streamer core - added RAM_STYLE parameter, implemented with SDP RAM... · f855ee52
  Lucian Petrica authored 4 years ago
  
  Updated streamer core - added RAM_STYLE parameter, implemented with SDP RAM when using just one stream
  f855ee52
Aug 10, 2020
- Cleaned up core xml, set all support levels to Production · 6c4e55b0
  Lucian Petrica authored 4 years ago
  
  6c4e55b0
Aug 01, 2020
- Modified RTL streamer and its instantiation template, removing need for Q_srl in decoupled mode · 8eda4b18
  Lucian Petrica authored 4 years ago
  
  8eda4b18
Jul 27, 2020
- [rtllib] Update component.xml for virtexuplusHBM devices · 841617c2
  Yaman Umuroglu authored 4 years ago
  
  841617c2
Mar 04, 2020
- Added RTL parameter streamer · 7ae7b281
  Lucian Petrica authored 5 years ago
  
  7ae7b281