Commits · 71a680a09dcd276f971c7c2094758353beb21aac · streichg / Finn · GitLab

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Sep 27, 2022
- [FIFO] SystemVerilog -> Verilog fix in Q_srl.v · a8d3fb6c
  Yaman Umuroglu authored 2 years ago
  
  a8d3fb6c
Sep 26, 2022
- [FIFO] SystemVerilog -> Verilog fix in Q_srl.v · dc830f11
  Yaman Umuroglu authored 2 years ago
  
  dc830f11
Sep 19, 2022
- [FIFO] add hw maxcount tracking to rtl FIFOs with opt attribute · e8f7c756
  Yaman Umuroglu authored 2 years ago
  
  e8f7c756
Jul 14, 2022
- Revert "Merge pull request #637 from Xilinx/dev" · 963fde53
  auphelia authored 2 years ago
  
  This reverts commit fe4a150c, reversing changes made to c98c2211.
  963fde53
Jun 29, 2022
- [Refactor] Change copyright header · 7750fbb0
  auphelia authored 2 years ago
  
  7750fbb0
Jun 28, 2022
- [Pre-commit] pre-commit fixes of axi-info tcl script and Jenkinsfile · fa2401a8
  auphelia authored 2 years ago
  
  fa2401a8
Jun 17, 2022
- Hotfix: Instance name for axi_info instantiation. · dd704a6c
  Thomas B. Preußer authored 2 years ago
  
  dd704a6c
May 31, 2022
- [finn-rtllib] Update ip for axi-info · 989fbdae
  auphelia authored 2 years ago
  
  989fbdae
May 30, 2022
- Fixed signature composition. · e88a0295
  Thomas B. Preußer authored 2 years ago
  
  e88a0295
May 25, 2022
- [finn rtllib] Add updated packaged ip for axi_info · d47a5599
  auphelia authored 2 years ago
  
  d47a5599
- axi_info read not to block upon out-of-bounds accesses. · 5d0da833
  Thomas B. Preußer authored 2 years ago
  
  5d0da833
May 24, 2022
- [Refactor] move checksum files to under custom_hls · dac25880
  Yaman Umuroglu authored 2 years ago
  
  dac25880
May 23, 2022
- Packaged IP infrastructure for axi_info. · f7173c99
  Thomas B. Preußer authored 2 years ago
  
  f7173c99
- [HLSCustomOp] generate separate sync/sim .dat files for decoupled · 833be8e1
  Yaman Umuroglu authored 2 years ago
  
  833be8e1
May 13, 2022
- Component to expose a compiled-in constant info space on AXI-lite. · 92c0171a
  Thomas B. Preußer authored 2 years ago
  
  92c0171a
May 12, 2022
- Corrected copyright. · bc572eef
  Thomas B. Preußer authored 2 years ago
  
  bc572eef
May 05, 2022
- Generic top-level macro customizable through command-line defines. · d20837db
  Thomas B. Preußer authored 2 years ago
  
  d20837db
May 04, 2022
- Prototype for checksumming over stream data. · 232464c7
  Thomas B. Preußer authored 2 years ago
  
  232464c7
Nov 30, 2021
- [Vitis] minor fixes for 2021.1 and Versal Prime parts · 91eaf3b1
  Yaman Umuroglu authored 3 years ago
  
  91eaf3b1
Sep 30, 2021
- Updated achritecture families to all current types, minus the CPLDs · bda18b3d
  john authored 3 years ago
  
  bda18b3d
Jul 02, 2021
- Converted *.v files from CRLF line endings to LF. · 486a94aa
  Hendrik Borras authored 3 years ago
  
  486a94aa
- Reverted .dat-file change and excluded .dat files trailing-whitespace hook · b9db2e2c
  Hendrik Borras authored 3 years ago
  
  b9db2e2c
Jun 25, 2021
- Applied new pre-commit-config to all files, potentially critical changes only · 51b95ca1
  Hendrik Borras authored 3 years ago
  
  51b95ca1
- Applied new pre-commit-config to all files, non-critical changes only · 3dc48c57
  Hendrik Borras authored 3 years ago
  
  3dc48c57
Dec 17, 2020
- [Release] merge dev into master for v0.5b · 4fee6ffd
  Yaman Umuroglu authored 4 years ago
  
  4fee6ffd
Oct 14, 2020
- [Docs] document flushing requirement after AXI lite read/write · c5c5f214
  Yaman Umuroglu authored 4 years ago
  
  c5c5f214
Oct 12, 2020
- Fixed signal assignment · 6eea8ddf
  Lucian Petrica authored 4 years ago
  
  6eea8ddf
- Fix for MEM_WIDTH==32 · 10dee40a
  Lucian Petrica authored 4 years ago
  
  10dee40a
- Some documentation for the streamer address map · 2df7959b
  Lucian Petrica authored 4 years ago
  
  2df7959b
- Added missing IP file · 735dca29
  Lucian Petrica authored 4 years ago
  
  735dca29
Oct 09, 2020
- Added AXILite interface for writing weights; tested in behavioural sim with 1 stream · ee57c98c
  Lucian Petrica authored 4 years ago
  
  ee57c98c
Sep 24, 2020
- Wired up config interface when depth=1 and nstreams <= 2 · 112c4705
  Lucian Petrica authored 4 years ago
  
  112c4705
Sep 21, 2020
- Implemented FIFO auto-sizing · 5d24f433
  Lucian Petrica authored 4 years ago
  
  5d24f433
Sep 17, 2020
- Added all synthesis source files to be used for simulation too · 27863700
  john authored 4 years ago
  
  27863700
Aug 21, 2020
- Updated streamer core - added RAM_STYLE parameter, implemented with SDP RAM... · f855ee52
  Lucian Petrica authored 4 years ago
  
  Updated streamer core - added RAM_STYLE parameter, implemented with SDP RAM when using just one stream
  f855ee52
Aug 12, 2020
- Implemented explicit solution for DEPTH=1 corner-case · f78176a6
  Lucian Petrica authored 4 years ago
  
  f78176a6
Aug 10, 2020
- Cleaned up core xml, set all support levels to Production · 6c4e55b0
  Lucian Petrica authored 4 years ago
  
  6c4e55b0
- Fixed address range of readmemh in rtl streamer · a1c1e14c
  Lucian Petrica authored 4 years ago
  
  a1c1e14c
Aug 01, 2020
- Modified RTL streamer and its instantiation template, removing need for Q_srl in decoupled mode · 8eda4b18
  Lucian Petrica authored 4 years ago
  
  8eda4b18
Jul 27, 2020
- [rtllib] Update component.xml for virtexuplusHBM devices · 841617c2
  Yaman Umuroglu authored 4 years ago
  
  841617c2