Commits · 60ddcb87c775b213f8e8142763457633230372ec · streichg / Finn · GitLab

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Apr 07, 2022
- [Deps] update qonnx · 60ddcb87
  Yaman Umuroglu authored 2 years ago
  
  Unverified
  
  60ddcb87
Mar 30, 2022
- Merge pull request #580 from jterry-x/dev · 26169798
  Yaman Umuroglu authored 2 years ago
  
  Add FPGA Flow tutorial
  Unverified
  
  26169798
Mar 28, 2022
- [Tutorial] enhancements and fixes to FPGA Flow tutorial · 9b2d9347
  Yaman Umuroglu authored 2 years ago
  
  9b2d9347
Mar 26, 2022
- Update README.md · 962516fb
  John Terry authored 2 years ago
  
  Attempt to match upstream.
  Unverified
  
  962516fb
- Updated for clarity and formatting · 24463a50
  john authored 2 years ago
  
  24463a50
- Created new tutorial for FPGA flow · 1012bb08
  john authored 2 years ago
  
  1012bb08
- Merge branch 'dev' of https://github.com/jterry-x/finn into dev · f3af5385
  john authored 2 years ago
  
  f3af5385
Mar 14, 2022
- [README] replace Gitter with GitHub Discussions · 26ad2933
  Yaman Umuroglu authored 3 years ago
  
  Unverified
  
  26ad2933
Feb 22, 2022
- Merge pull request #552 from mmrahorovic/fix_pre_commit · fd45721c
  Yaman Umuroglu authored 3 years ago
  
  Changes to pre-commit YAML file
  Unverified
  
  fd45721c
Feb 17, 2022
- [pre-commit]: minor changes to coding style · 1fed0b88
  mmrahorovic authored 3 years ago
  
  1fed0b88
- [requirements]: update pre-commit · 8da17559
  mmrahorovic authored 3 years ago
  
  8da17559
- [pre-commit]: update to repo · a6cbbfa5
  mmrahorovic authored 3 years ago
  
  a6cbbfa5
Jan 13, 2022
- Merge pull request #491 from volcacius/gpu_mlp_brevitas_notebook · 963aba18
  Yaman Umuroglu authored 3 years ago
  
  GPU training support for the cybersecurity MLP notebook
  Unverified
  
  963aba18
- Fix scaling_impl_type in final inference layer · b38d7361
  Alessandro Pappalardo authored 3 years ago
  
  Signed-off-by: Alessandro Pappalardo <volcacius@users.noreply.github.com>
  b38d7361
- GPU training support for the cybersecurity example · 67a2fabc
  Alessandro Pappalardo authored 3 years ago
  
  Signed-off-by: Alessandro Pappalardo <volcacius@users.noreply.github.com>
  67a2fabc
Nov 24, 2021
- Merge pull request #451 from Xilinx/feature/pool_flex · 30aa49f3
  Yaman Umuroglu authored 3 years ago
  
  Make Pool_Batch more flexible
  Unverified
  
  30aa49f3
- [Deps] update hlslib · 7a12c616
  Yaman Umuroglu authored 3 years ago
  
  7a12c616
- [Test] enable 1D tests + restructure convert_to_hls_pool_batch · 63f52f19
  Yaman Umuroglu authored 3 years ago
  
  63f52f19
- [Pool] more steps towards non-square support, square imgs working again · 123892ff
  Yaman Umuroglu authored 3 years ago
  
  123892ff
Nov 23, 2021
- [ConvertToHLS] round of fixes to allow non-square pool, not yet done · 61b349f9
  Yaman Umuroglu authored 3 years ago
  
  61b349f9
- [Test] support creating 1d maxpool in convert_to_hls_pool_batch · b6a5b35e
  Yaman Umuroglu authored 3 years ago
  
  b6a5b35e
- [Pool] change Pool_Batch to use kernel size as list, not scalar · eb2652af
  Yaman Umuroglu authored 3 years ago
  
  eb2652af
- [Pool] adjust kernel param as total k · 18d17bfd
  Yaman Umuroglu authored 3 years ago
  
  18d17bfd
- [Deps] update hlslib · 4b93d77b
  Yaman Umuroglu authored 3 years ago
  
  4b93d77b
Nov 20, 2021
- Merge pull request #443 from Xilinx/feature/concat · 11df4ba2
  Yaman Umuroglu authored 3 years ago
  
  Streaming Concat op support
  Unverified
  
  11df4ba2
Nov 19, 2021
- [Vitis] don't call layout inference in VitisBuild · fb3a8237
  Yaman Umuroglu authored 3 years ago
  
  fb3a8237
- [Build] better resolution for unspec'd Vitis platform for Alveo · d6ca2e2e
  Yaman Umuroglu authored 3 years ago
  
  d6ca2e2e
Nov 15, 2021
- [Hotfix] remove extras=True for tests in setup.cfg · 29d4d790
  Yaman Umuroglu authored 3 years ago
  
  29d4d790
Nov 13, 2021
- [SetFolding] handle ConvolutionInputGenerator1D as well · cc648647
  Yaman Umuroglu authored 3 years ago
  
  cc648647
- [Build] pass large_fifo_mem_style correctly · ae5cb636
  Yaman Umuroglu authored 3 years ago
  
  ae5cb636
- [SWG] no parallel window output with bram/uram ram_style from 1D SWG · 61a293a3
  Yaman Umuroglu authored 3 years ago
  
  61a293a3
Nov 12, 2021
- [Test] add ipstitch+rtlsim test for concat · 067d165b
  Yaman Umuroglu authored 3 years ago
  
  067d165b
- [Deps] update finn-base · db37e945
  Yaman Umuroglu authored 3 years ago
  
  db37e945
- [Infra] don't install extras pkgs during test · 5e7a2ce1
  Yaman Umuroglu authored 3 years ago
  
  5e7a2ce1
- [Concat] make both cppsim and rtl/stitched-ip rtlsim work · 7a5146c4
  Yaman Umuroglu authored 3 years ago
  
  7a5146c4
- [Stitch] gen hierarchical util report if synthesized dcp · 529bc249
  Yaman Umuroglu authored 3 years ago
  
  529bc249
- [Concat] allow indexing get_input_datatype, does nothing though · 14206f6f
  Yaman Umuroglu authored 3 years ago
  
  14206f6f
- [InsertFIFO] fixes when first node has multiple inputs · 8827ab97
  Yaman Umuroglu authored 3 years ago
  
  8827ab97
Nov 10, 2021
- [SWG] updates to ConvolutionInputGenerator1D resource estimates · 1c37c8d7
  Yaman Umuroglu authored 3 years ago
  
  1c37c8d7
- [Stitch] fix ext interface ordering for multi-I/O · c251fbc5
  Yaman Umuroglu authored 3 years ago
  
  c251fbc5