This reverts commit fe4a150c, reversing
changes made to c98c2211.

This reverts commit b419957e.

* Added transform to set mem modes

* Add transform to set folding (SIMD/PE)

* Implemented resource allocation transform and test

* Reverted to version in dev

* Updated expected resource counts in res estimate test

* Added URAM and DSP resource estimates; changed FC layer resType to lut/dsp, made it optional, and made lut the default

* Correct handling of URAM

* Fixed resource estimation for fc layer

* Fixed uram estimation in SWU

* Fixed res estimate test

* Added resource estimation to VVAU, and changed resType to same pattern in FClayer; fixed DSP estimation in FClayer

* Fixes for VVAU resource estimation

* Updated SWU memory estimate; modified folding transform for correct depthwise SWU folding

* Moved folding transforms out of PR branch

* Removed files added by mistake in merge

* Fixed test

* [Deps, Refactor] update finn-base, move create.py back into finn

* [Deps] update finn-base to get optional, restricted-value attributes

* [HLSCustomOp] specify allowed values for HLSCustomOps where appropriate

* [Deps] update finn-base and Brevitas

Co-authored-by: Yaman Umuroglu <maltanar@gmail.com>

* [Refactor] use getCustomOp instead of direct registry access

* [Refactor] move HLSCustomOp base to own file

* [Refactor] register all HLSCustomOps in new style

* [Refactor] use correct domain for custom ops acc. to new style

* [Deps] update finn-base to get new-style customop domains

* [Refactor] more domain fixes

* [Test] fix ipstitch expected io values in rtlsim

* [Deps] update finn-base and brevitas

* [Docs] link to CustomOp reorg PR

so that we can run it with the correct parallelization method in the test suite

slight difference from others: needs ReplaceVerilogRelPaths