Commits · 5cc755603e1796b14c64136fc368ad29a922b787 · streichg / Finn · GitLab

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Jun 25, 2021
- Applied new pre-commit-config to all files, non-critical changes only · 3dc48c57
  Hendrik Borras authored 3 years ago
  
  3dc48c57
Dec 17, 2020
- [Release] merge dev into master for v0.5b · 4fee6ffd
  Yaman Umuroglu authored 4 years ago
  
  4fee6ffd
Oct 12, 2020
- [Tests] add missing license header to a few tests · 1ad94b9a
  Yaman Umuroglu authored 4 years ago
  
  1ad94b9a
Sep 10, 2020
- [Refactor] ReplaceVerilogRelPaths called automatically · 1ca32bb6
  Yaman Umuroglu authored 4 years ago
  
  1ca32bb6
Jun 25, 2020
- [Test] Add rtlsim · 06a0b610
  Tobi-Alonso authored 4 years ago
  
  06a0b610
- [FPGADataflow] Add scalar parameter broadcast to InferChannelwiseLinearLayer · d216d85f
  Tobi-Alonso authored 4 years ago
  
  d216d85f
Jun 24, 2020
- [TEST] Add idt== DataType.INT32 test case · 3f8b7e7c
  Tobi-Alonso authored 4 years ago
  
  3f8b7e7c
- [Test] Add test for InferChannelwiseLinearLayer · fcdd18bb
  Tobi-Alonso authored 4 years ago
  
  fcdd18bb