Updated streamer core - added RAM_STYLE parameter, implemented with SDP RAM...

Updated streamer core - added RAM_STYLE parameter, implemented with SDP RAM when using just one stream

finn-rtllib/memstream/component.xml

@@ -260,7 +260,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>274387f2</spirit:value>
+            <spirit:value>083f6ff3</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -290,7 +290,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>198c09a6</spirit:value>
+            <spirit:value>d714c73b</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -780,6 +780,11 @@
         <spirit:displayName>Mem Init</spirit:displayName>
         <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.MEM_INIT">./</spirit:value>
       </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>RAM_STYLE</spirit:name>
+        <spirit:displayName>Ram Style</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.RAM_STYLE">auto</spirit:value>
+      </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>STRM0_WIDTH</spirit:name>
         <spirit:displayName>Strm0 Width</spirit:displayName>
@@ -873,6 +878,12 @@
     </spirit:modelParameters>
   </spirit:model>
   <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_44c459b8</spirit:name>
+      <spirit:enumeration>auto</spirit:enumeration>
+      <spirit:enumeration>block</spirit:enumeration>
+      <spirit:enumeration>distributed</spirit:enumeration>
+    </spirit:choice>
     <spirit:choice>
       <spirit:name>choice_list_9d8b0d81</spirit:name>
       <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
@@ -906,6 +917,12 @@
         <spirit:userFileType>CHECKSUM_9425c051</spirit:userFileType>
         <spirit:logicalName>xil_defaultlib</spirit:logicalName>
       </spirit:file>
+      <spirit:file>
+        <spirit:name>hdl/ramb18_sdp.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_9e2eda76</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
       <spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
@@ -919,7 +936,7 @@
       <spirit:file>
         <spirit:name>xgui/memstream_v1_0.tcl</spirit:name>
         <spirit:fileType>tclSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_92c3ebfc</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_d714c73b</spirit:userFileType>
         <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
@@ -1045,6 +1062,11 @@
       <spirit:name>Component_Name</spirit:name>
       <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">memstream_v1_0</spirit:value>
     </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RAM_STYLE</spirit:name>
+      <spirit:displayName>Ram Style</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RAM_STYLE" spirit:choiceRef="choice_list_44c459b8">auto</spirit:value>
+    </spirit:parameter>
   </spirit:parameters>
   <spirit:vendorExtensions>
     <xilinx:coreExtensions>
@@ -1060,16 +1082,16 @@
       <xilinx:displayName>memstream_v1_0</xilinx:displayName>
       <xilinx:autoFamilySupportLevel>level_0</xilinx:autoFamilySupportLevel>
       <xilinx:definitionSource>package_project</xilinx:definitionSource>
-      <xilinx:coreRevision>4</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2020-08-10T17:17:33Z</xilinx:coreCreationDateTime>
+      <xilinx:coreRevision>9</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2020-08-21T11:26:48Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
       <xilinx:xilinxVersion>2020.1</xilinx:xilinxVersion>
       <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="6d8b2551"/>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="9af3afa8"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="fe9e02ac"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="cabd7433"/>
-      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="f63127c8"/>
-      <xilinx:checksum xilinx:scope="parameters" xilinx:value="5365a08b"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="29c70cc4"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="858b58f8"/>
     </xilinx:packagingInfo>
   </spirit:vendorExtensions>
 </spirit:component>

finn-rtllib/memstream/hdl/memstream_singleblock.v

@@ -35,7 +35,7 @@
 module memstream_singleblock
 #(
     parameter CONFIG_EN = 1,
-    parameter NSTREAMS = 2,//1 up to 6
+    parameter NSTREAMS = 2,//1 up to 2
 
     parameter MEM_DEPTH = 512,
     parameter MEM_WIDTH = 32,
@@ -63,8 +63,8 @@ module memstream_singleblock
 	input [31:0] config_address,
 	input config_ce,
 	input config_we,
-	input [31:0] config_d0,
-	output [31:0] config_q0,
+	input [MEM_WIDTH-1:0] config_d0,
+	output [MEM_WIDTH-1:0] config_q0,
 
     //multiple output AXI Streams, TDATA width rounded to multiple of 8 bits
     input m_axis_0_tready,
@@ -104,13 +104,8 @@ if(MEM_DEPTH > 1) begin: use_ram
 localparam BLOCKADRWIDTH = $clog2(MEM_DEPTH);
 
 reg [BLOCKADRWIDTH-1:0] strm0_addr = STRM0_OFFSET;
-reg [BLOCKADRWIDTH-1:0] strm1_addr = STRM1_OFFSET;
-
 wire strm0_rst;
-wire strm1_rst;
-
 assign strm0_rst = strm0_incr_en & (strm0_addr == (STRM0_OFFSET + STRM0_DEPTH-1));
-assign strm1_rst = strm1_incr_en & (strm1_addr == (STRM1_OFFSET + STRM1_DEPTH-1));
 
 //one address counter per stream; more LUTs but keeps routing short and local
 always @(posedge aclk) begin
@@ -118,6 +113,42 @@ always @(posedge aclk) begin
         strm0_addr <= STRM0_OFFSET;
     else if(strm0_incr_en)
         strm0_addr <= strm0_addr + 1;
+end
+
+if(NSTREAMS == 1) begin: sdp
+
+ramb18_sdp
+#(
+    .ID(0),
+	.DWIDTH(MEM_WIDTH),
+	.AWIDTH(BLOCKADRWIDTH),
+    .DEPTH(MEM_DEPTH),
+	.MEM_INIT(MEM_INIT),
+    .RAM_STYLE(RAM_STYLE)
+)
+ram
+(
+	.clk(aclk),
+
+    .ena(config_ce),
+	.wea(config_we),
+	.addra(config_address[BLOCKADRWIDTH-1:0]),
+    .wdataa(config_d0),
+
+    .enb(strm0_incr_en),
+    .enqb(strm0_incr_en),
+	.addrb(strm0_addr),
+	.rdqb(m_axis_0_tdata)
+);
+
+
+end else begin: tdp
+
+reg [BLOCKADRWIDTH-1:0] strm1_addr = STRM1_OFFSET;
+wire strm1_rst;
+assign strm1_rst = strm1_incr_en & (strm1_addr == (STRM1_OFFSET + STRM1_DEPTH-1));
+
+always @(posedge aclk) begin
     if(strm1_rst | rst)
         strm1_addr <= STRM1_OFFSET;
     else if(strm1_incr_en)
@@ -152,6 +183,8 @@ ram
 	.rdqb(m_axis_1_tdata)
 );
 
+end
+
 end else begin: bypass
 
 reg [MEM_WIDTH-1:0] singleval[0:0];

finn-rtllib/memstream/hdl/ramb18_sdp.v

+/*
+ Copyright (c) 2020, Xilinx
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice, this
+   list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright notice,
+   this list of conditions and the following disclaimer in the documentation
+   and/or other materials provided with the distribution.
+
+ * Neither the name of FINN nor the names of its
+   contributors may be used to endorse or promote products derived from
+   this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+module ramb18_sdp
+#(
+    parameter ID = 0,
+    parameter DWIDTH = 18,
+    parameter AWIDTH = 10,
+    parameter DEPTH = 2**AWIDTH,
+    parameter MEM_INIT = "",
+    parameter RAM_STYLE = "auto"
+)
+(
+	input clk,
+
+	input ena,
+	input wea,
+	input [AWIDTH-1:0] addra,
+	input [DWIDTH-1:0] wdataa,
+
+    input enb,
+    input enqb,
+	input [AWIDTH-1:0] addrb,
+	output reg [DWIDTH-1:0] rdqb
+);
+
+(* ram_style = RAM_STYLE *) reg [DWIDTH-1:0] mem[0:DEPTH-1];
+reg [DWIDTH-1:0] rdatab;
+
+`ifdef SYNTHESIS
+reg [7:0] idx = ID;
+`else
+reg [15:0] idx;
+`endif
+
+//initialize memory
+initial begin
+  //note the hacky way of adding a filename memblock_ID.dat to the path provided in MEM_INIT
+  //ID can go up to 99
+  if (ID < 0 && ID > 99) begin
+    $display("ID out of range [0-99]");
+    $finish();
+  end
+	//MEM_INIT path must be terminated by /
+  `ifdef SYNTHESIS
+  if (ID < 10)
+    $readmemh({MEM_INIT,"memblock_",idx+8'd48,".dat"}, mem, 0, DEPTH-1);
+  else
+    $readmemh({MEM_INIT,"memblock_",(idx/10)+8'd48,(idx%10)+8'd48,".dat"}, mem, 0, DEPTH-1);
+  `else
+  $sformat(idx,"%0d",ID);
+  if (ID < 10)
+    $readmemh({MEM_INIT,"memblock_",idx[7:0],".dat"}, mem, 0, DEPTH-1);
+  else
+    $readmemh({MEM_INIT,"memblock_",idx,".dat"}, mem, 0, DEPTH-1);
+  `endif
+end
+
+//memory ports, with output pipeline register
+always @(posedge clk) begin
+    if(wea)
+        mem[addra] <= wdataa;
+    if(enb)
+        rdatab <= mem[addrb];
+    if(enqb)
+        rdqb <= rdatab;
+end
+
+endmodule