src/finn/analysis/fpgadataflow/hls_synth_res_estimation.py

src/finn/analysis/fpgadataflow/res_estimation.py

src/finn/transformation/fpgadataflow/cleanup.py

src/finn/transformation/fpgadataflow/codegen_ipgen.py

src/finn/transformation/fpgadataflow/codegen_npysim.py

src/finn/transformation/fpgadataflow/compile.py

src/finn/transformation/fpgadataflow/hlssynth_ipgen.py

src/finn/transformation/fpgadataflow/insert_dwc.py

src/finn/transformation/fpgadataflow/prepare_rtlsim.py

...n/transformation/fpgadataflow/replace_verilog_relpaths.py

src/finn/transformation/fpgadataflow/set_exec_mode.py