Merge branch 'feature/decoupled_ram_style' into dev

finn-rtllib/memstream/hdl/ramb18_wf_dualport.v

@@ -33,7 +33,8 @@ module ramb18_wf_dualport
     parameter ID = 0,
 	parameter DWIDTH = 18,
 	parameter AWIDTH = 10,
-	parameter MEM_INIT = ""
+	parameter MEM_INIT = "",
+  parameter RAM_STYLE = "auto"
 )
 (
 	input clk,
@@ -49,7 +50,7 @@ module ramb18_wf_dualport
 	output reg [DWIDTH-1:0] rdqb
 );
 
-(* ram_style = "block" *) reg [DWIDTH-1:0] mem[0:2**AWIDTH-1];
+(* ram_style = RAM_STYLE *) reg [DWIDTH-1:0] mem[0:2**AWIDTH-1];
 reg [DWIDTH-1:0] rdataa;
 reg [DWIDTH-1:0] rdatab;
 

src/finn/custom_op/fpgadataflow/streamingfclayer_batch.py

@@ -92,6 +92,12 @@ class StreamingFCLayer_Batch(HLSCustomOp):
             # const -- embedded weights, default, long compile/synth times
             # decoupled -- streaming weights
             "mem_mode": ("s", False, "const"),
+            # FPGA resource type for memories in decoupled mode
+            # auto -- let Vivado decide
+            # block -- use BRAM
+            # distributed -- use LUTRAM
+            # see also https://www.xilinx.com/support/answers/38070.html
+            "ram_style": ("s", False, "auto"),
         }
         my_attrs.update(super().get_nodeattr_types())
         return my_attrs
@@ -983,6 +989,7 @@ class StreamingFCLayer_Batch(HLSCustomOp):
             self.code_gen_dict["$MEM_DEPTH$"] = [
                 str(roundup_to_integer_multiple(self.calc_wmem(), 1024))
             ]
+            self.code_gen_dict["$RAM_STYLE$"] = [self.get_nodeattr("ram_style")]
 
             template = self.decoupled_wrapper
 

src/finn/custom_op/fpgadataflow/templates.py

@@ -188,6 +188,7 @@ memstream
 .MEM_DEPTH($MEM_DEPTH$),
 .MEM_WIDTH($WEIGHT_WIDTH$),
 .MEM_INIT("./"),
+.RAM_STYLE("$RAM_STYLE$"),
 
 //widths per stream
 .STRM0_WIDTH($WEIGHT_WIDTH$),

tests/end2end/test_end2end_tfc_w1a1.py

@@ -137,6 +137,7 @@ def test_end2end_tfc_w1a1_fold_and_tlastmarker():
     fc0w.set_nodeattr("SIMD", 16)
     fc0w.set_nodeattr("PE", 16)
     fc0w.set_nodeattr("outFIFODepth", 4)
+    fc0w.set_nodeattr("ram_style", "block")
     fc1w.set_nodeattr("SIMD", 8)
     fc1w.set_nodeattr("PE", 8)
     fc1w.set_nodeattr("outFIFODepth", 4)
@@ -146,6 +147,7 @@ def test_end2end_tfc_w1a1_fold_and_tlastmarker():
     fc3w.set_nodeattr("SIMD", 16)
     fc3w.set_nodeattr("PE", 10)
     fc3w.set_nodeattr("outFIFODepth", 50)
+    fc3w.set_nodeattr("ram_style", "distributed")
     model = model.transform(InsertDWC())
     model = model.transform(InsertTLastMarker())
     model = model.transform(GiveUniqueNodeNames())