Add ap_ctrl_none back

custom_hls/accl/funcs.hpp

@@ -38,6 +38,17 @@ void accl_out(
     bool leftover = num_bits % accl_width != 0;
     int num_transfer_bits = ((num_bits + accl_width - 1) / accl_width) * accl_width;
 
+    unsigned int data_from_cclo_id = 9;
+
+    // Currently the hls driver does not allow us to make an async call, so we have to do
+    // it manually.
+    accl.start_call(
+        ACCL_SEND, num_transfer_bits / 32,
+        comm_adr, dest_rank, 0, data_from_cclo_id,
+        dpcfg_adr, cflags, sflags | 0x2,
+        0, 0, 0
+    );
+
     send: for (int i = 0; i < num_bits - step + 1; i += step) {
         if (i % stream_width == 0) {
             stream_word = in.read();
@@ -57,18 +68,6 @@ void accl_out(
         data.push(accl_word, 0);
     }
 
-
-    unsigned int data_from_cclo_id = 9;
-
-    // Currently the hls driver does not allow us to make an async call, so we have to do
-    // it manually.
-    accl.start_call(
-        ACCL_SEND, num_transfer_bits / 32,
-        comm_adr, dest_rank, 0, data_from_cclo_id, 
-        dpcfg_adr, cflags, sflags | 0x2, 
-        0, 0, 0
-    );
-
 #ifdef CPPSIM
     std::cerr << "accl_out waiting on ack" << std::endl;
 #endif

notebooks/end2end_example/cybersecurity/build_accl.py

@@ -41,7 +41,7 @@ steps = [
     "step_generate_estimate_reports",
     "step_hls_codegen",
     "step_hls_ipgen",
-    # "step_set_fifo_depths",
+    "step_set_fifo_depths",
     "step_create_stitched_ip",
 ]
 
@@ -61,7 +61,7 @@ cfg_splits = build.DataflowBuildConfig(
     shell_flow_type     = build_cfg.ShellFlowType.VITIS_ALVEO,
     board               = "U55C",
     num_boards          = 2,
-    # start_step="step_create_stitched_ip",
+    # start_step="step_set_fifo_depths",
     save_intermediate_models = True,
 )
 

src/finn/custom_op/fpgadataflow/accl.py

@@ -226,7 +226,7 @@ class ACCLOut(ACCLOp):
             '#pragma HLS INTERFACE axis port=in0_{}'.format(self.hls_sname()),
             "#pragma HLS INTERFACE s_axilite port=dpcfg_adr bundle=control",
             "#pragma HLS INTERFACE s_axilite port=comm_adr bundle=control",
-            "#pragma HLS INTERFACE s_axilite port=return bundle=control",
+            "#pragma HLS INTERFACE ap_ctrl_none port=return",
         ]
 
     def strm_decl(self):
@@ -280,18 +280,19 @@ class ACCLOut(ACCLOp):
         dest = self.get_nodeattr("otherRank")
 
         self.code_gen_dict["$DOCOMPUTE$"] = [
-            '''
-            accl_out<{}, {}, {}>(
-                {},
-                comm_adr,
-                dpcfg_adr,
-                cmd_to_cclo,
-                sts_from_cclo,
-                data_to_cclo,
-                in0_{},
-                wait_for_ack
-            );'''.format(stream_width, num_bits, step, dest, self.hls_sname()),
-            '''
+            f'''
+            if (!in0_{self.hls_sname()}.empty()) {{
+                accl_out<{stream_width}, {num_bits}, {step}>(
+                    {dest},
+                    comm_adr,
+                    dpcfg_adr,
+                    cmd_to_cclo,
+                    sts_from_cclo,
+                    data_to_cclo,
+                    in0_{self.hls_sname()},
+                    wait_for_ack
+                );
+            }}
             #ifdef CPPSIM
             cclo->stop();
             #endif
@@ -536,7 +537,8 @@ class ACCLIn(ACCLOp):
         self.code_gen_dict["$BLACKBOXFUNCTION$"] = [
             '''void {}(
                 STREAM<stream_word> &data_from_cclo,
-                hls::stream<ap_uint<{}>> &out_{}
+                hls::stream<ap_uint<{}>> &out_{},
+                int dummy
             )''' .format(
                 self.onnx_node.name,
                 self.get_outstream_width(),

src/finn/transformation/fpgadataflow/create_stitched_ip.py

@@ -87,7 +87,7 @@ class CreateStitchedIP(Transformation):
     The packaged block design IP can be found under the ip subdirectory.
     """
 
-    def __init__(self, fpgapart, clk_ns, ip_name="finn_design", vitis=False, signature=[]):
+    def __init__(self, fpgapart, clk_ns, ip_name="finn_design", vitis=False, signature=[], skip_accl_interface=False):
         super().__init__()
         self.fpgapart = fpgapart
         self.clk_ns = clk_ns
@@ -111,6 +111,7 @@ class CreateStitchedIP(Transformation):
             "aximm": [],
             "axilite": [],
         }
+        self.skip_accl_interface = skip_accl_interface
 
     def connect_clk_rst(self, node):
         inst_name = node.name
@@ -450,7 +451,7 @@ class CreateStitchedIP(Transformation):
             issubclass(type(getCustomOp(node)), ACCLOp)
             for node in model.graph.node
         )
-        if has_accl_node:
+        if has_accl_node and not self.skip_accl_interface:
             self.setup_accl_interface(model)
 
         if self.signature:

src/finn/transformation/fpgadataflow/set_fifo_depths.py

@@ -315,7 +315,7 @@ class InsertAndSetFIFODepths(Transformation):
         max_cycles = perf["max_cycles"]
         model = model.transform(PrepareIP(self.fpgapart, self.clk_ns))
         model = model.transform(HLSSynthIP())
-        model = model.transform(CreateStitchedIP(self.fpgapart, self.clk_ns))
+        model = model.transform(CreateStitchedIP(self.fpgapart, self.clk_ns, skip_accl_interface=True))
         model.set_metadata_prop("exec_mode", "rtlsim")
 
         if self.force_python_sim: