[HLSCustomOp] add base class methods for Verilog fnames/paths

src/finn/custom_op/fpgadataflow/__init__.py

@@ -109,34 +109,45 @@ class HLSCustomOp(CustomOp):
         )
         return verilog_file
 
-    def prepare_rtlsim(self):
-        """Creates a Verilator emulation library for the RTL code generated
-        for this node, sets the rtlsim_so attribute to its path and returns
-        a PyVerilator wrapper around it."""
+    def get_all_verilog_paths(self):
+        "Return list of all folders containing Verilog code for this node."
 
-        if PyVerilator is None:
-            raise ImportError("Installation of PyVerilator is required.")
-        # ensure that code is generated
         code_gen_dir = self.get_nodeattr("code_gen_dir_ipgen")
         assert (
             code_gen_dir != ""
         ), """Node attribute "code_gen_dir_ipgen" is
         not set. Please run HLSSynthIP first."""
-
         verilog_path = "{}/project_{}/sol1/impl/verilog/".format(
             code_gen_dir, self.onnx_node.name
         )
+        # default impl only returns the HLS verilog codegen dir
+        return [verilog_path]
+
+    def get_all_verilog_filenames(self):
+        "Return list of all Verilog files used for this node."
 
         verilog_files = []
-        for f in os.listdir(verilog_path):
-            if f.endswith(".v"):
-                verilog_files += [f]
+        verilog_paths = self.get_all_verilog_paths()
+        for verilog_path in verilog_paths:
+            for f in os.listdir(verilog_path):
+                if f.endswith(".v"):
+                    verilog_files += [f]
+        return verilog_files
 
+    def prepare_rtlsim(self):
+        """Creates a Verilator emulation library for the RTL code generated
+        for this node, sets the rtlsim_so attribute to its path and returns
+        a PyVerilator wrapper around it."""
+
+        if PyVerilator is None:
+            raise ImportError("Installation of PyVerilator is required.")
+        verilog_paths = self.get_all_verilog_paths()
+        verilog_files = self.get_all_verilog_filenames()
         # build the Verilator emu library
         sim = PyVerilator.build(
             verilog_files,
             build_dir=make_build_dir("pyverilator_" + self.onnx_node.name + "_"),
-            verilog_path=[verilog_path],
+            verilog_path=verilog_paths,
             trace_depth=get_rtlsim_trace_depth(),
             top_module_name=self.get_verilog_top_module_name(),
         )