Merge pull request #635 from fpjentzsch/ooc
Fix OOC synth, add System Verilog support
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- fetch-repos.sh 1 addition, 1 deletionfetch-repos.sh
- src/finn/transformation/fpgadataflow/create_stitched_ip.py 3 additions, 2 deletionssrc/finn/transformation/fpgadataflow/create_stitched_ip.py
- src/finn/transformation/fpgadataflow/synth_ooc.py 1 addition, 1 deletionsrc/finn/transformation/fpgadataflow/synth_ooc.py
- src/finn/util/pyverilator.py 3 additions, 1 deletionsrc/finn/util/pyverilator.py
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