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Commit 7f1d57ab authored by auphelia's avatar auphelia
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Merge branch 'dev' into feature/cnv_end2end_test

parents e7c6016a e02dc5bd
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src/finn/custom_op/fpgadataflow/convolutioninputgenerator.py
+ 9
− 9
View file @ 7f1d57ab
......@@ -138,7 +138,7 @@ class ConvolutionInputGenerator(HLSCustomOp):
"""Returns FINN DataType of output."""
return DataType[self.get_nodeattr("outputDataType")]
def get_in_stream_width(self):
def get_instream_width(self):
"""Returns stream width, input and output stream width are equal for
the sliding window function"""
ibits = self.get_input_datatype().bitwidth()
......@@ -147,11 +147,11 @@ class ConvolutionInputGenerator(HLSCustomOp):
assert simd == ifm_ch, "SWG currently requires SIMD=IFM"
return simd * ibits
def get_out_stream_width(self):
def get_outstream_width(self):
"""Returns stream width, input and output stream width are equal for
the sliding window function, so the function to determine the input
stream width can be reused."""
return self.get_in_stream_width()
return self.get_instream_width()
def get_number_output_values(self):
folded_oshape = self.get_folded_output_shape()
......@@ -212,7 +212,7 @@ class ConvolutionInputGenerator(HLSCustomOp):
code_gen_dir, node.name, prefixed_top_name
)
if os.path.isfile(verilog_file):
nbits = self.get_in_stream_width()
nbits = self.get_instream_width()
rtlsim_inp = npy_to_rtlsim_input(
"{}/input_0.npy".format(code_gen_dir), export_idt, nbits
)
......@@ -229,7 +229,7 @@ class ConvolutionInputGenerator(HLSCustomOp):
rtlsim_output = self.rtlsim(sim, rtlsim_inp)
odt = export_idt
target_bits = odt.bitwidth()
packed_bits = self.get_out_stream_width()
packed_bits = self.get_outstream_width()
out_npy_path = "{}/output.npy".format(code_gen_dir)
out_shape = self.get_folded_output_shape()
rtlsim_output_to_npy(
......@@ -293,7 +293,7 @@ class ConvolutionInputGenerator(HLSCustomOp):
# use binary for bipolar storage
dtype = DataType.BINARY
elem_bits = dtype.bitwidth()
packed_bits = self.get_in_stream_width()
packed_bits = self.get_instream_width()
packed_hls_type = "ap_uint<%d>" % packed_bits
elem_hls_type = dtype.get_hls_datatype_str()
npy_type = "float"
......@@ -307,10 +307,10 @@ class ConvolutionInputGenerator(HLSCustomOp):
def strm_decl(self):
self.code_gen_dict["$STREAMDECLARATIONS$"] = []
self.code_gen_dict["$STREAMDECLARATIONS$"].append(
'hls::stream<ap_uint<{}>> in0 ("in0");'.format(self.get_in_stream_width())
'hls::stream<ap_uint<{}>> in0 ("in0");'.format(self.get_instream_width())
)
self.code_gen_dict["$STREAMDECLARATIONS$"].append(
'hls::stream<ap_uint<{}>> out ("out");'.format(self.get_out_stream_width())
'hls::stream<ap_uint<{}>> out ("out");'.format(self.get_outstream_width())
)
def docompute(self):
......@@ -329,7 +329,7 @@ class ConvolutionInputGenerator(HLSCustomOp):
# use binary for bipolar storage
dtype = DataType.BINARY
elem_bits = dtype.bitwidth()
packed_bits = self.get_out_stream_width()
packed_bits = self.get_outstream_width()
packed_hls_type = "ap_uint<%d>" % packed_bits
elem_hls_type = dtype.get_hls_datatype_str()
npy_type = "float"
......
src/finn/custom_op/fpgadataflow/streamingdatawidthconverter_batch.py
+ 10
− 10
View file @ 7f1d57ab
......@@ -118,10 +118,10 @@ class StreamingDataWidthConverter_Batch(HLSCustomOp):
folded_ishape = self.get_folded_input_shape()
return np.prod(folded_ishape[:-1])
def get_in_stream_width(self):
def get_instream_width(self):
return self.get_nodeattr("inWidth")
def get_out_stream_width(self):
def get_outstream_width(self):
return self.get_nodeattr("outWidth")
def make_shape_compatible_op(self, model):
......@@ -204,7 +204,7 @@ class StreamingDataWidthConverter_Batch(HLSCustomOp):
# use binary for bipolar storage
dtype = DataType.BINARY
elem_bits = dtype.bitwidth()
packed_bits = self.get_in_stream_width()
packed_bits = self.get_instream_width()
packed_hls_type = "ap_uint<%d>" % packed_bits
elem_hls_type = dtype.get_hls_datatype_str()
npy_type = "float"
......@@ -218,10 +218,10 @@ class StreamingDataWidthConverter_Batch(HLSCustomOp):
def strm_decl(self):
self.code_gen_dict["$STREAMDECLARATIONS$"] = []
self.code_gen_dict["$STREAMDECLARATIONS$"].append(
'hls::stream<ap_uint<{}>> in0 ("in0");'.format(self.get_in_stream_width())
'hls::stream<ap_uint<{}>> in0 ("in0");'.format(self.get_instream_width())
)
self.code_gen_dict["$STREAMDECLARATIONS$"].append(
'hls::stream<ap_uint<{}>> out ("out");'.format(self.get_out_stream_width())
'hls::stream<ap_uint<{}>> out ("out");'.format(self.get_outstream_width())
)
def docompute(self):
......@@ -238,7 +238,7 @@ class StreamingDataWidthConverter_Batch(HLSCustomOp):
# use binary for bipolar storage
dtype = DataType.BINARY
elem_bits = dtype.bitwidth()
packed_bits = self.get_out_stream_width()
packed_bits = self.get_outstream_width()
packed_hls_type = "ap_uint<%d>" % packed_bits
elem_hls_type = dtype.get_hls_datatype_str()
npy_type = "float"
......@@ -262,9 +262,9 @@ class StreamingDataWidthConverter_Batch(HLSCustomOp):
self.code_gen_dict["$SAVEASCNPY$"] = []
def blackboxfunction(self):
in_packed_bits = self.get_in_stream_width()
in_packed_bits = self.get_instream_width()
in_packed_hls_type = "ap_uint<%d>" % in_packed_bits
out_packed_bits = self.get_out_stream_width()
out_packed_bits = self.get_outstream_width()
out_packed_hls_type = "ap_uint<%d>" % out_packed_bits
self.code_gen_dict["$BLACKBOXFUNCTION$"] = [
"void %s(hls::stream<%s > &in0, hls::stream<%s > &out)"
......@@ -327,7 +327,7 @@ class StreamingDataWidthConverter_Batch(HLSCustomOp):
code_gen_dir, node.name, prefixed_top_name
)
if os.path.isfile(verilog_file):
nbits = self.get_in_stream_width()
nbits = self.get_instream_width()
rtlsim_inp = npy_to_rtlsim_input(
"{}/input_0.npy".format(code_gen_dir), export_idt, nbits
)
......@@ -344,7 +344,7 @@ class StreamingDataWidthConverter_Batch(HLSCustomOp):
rtlsim_output = self.rtlsim(sim, rtlsim_inp)
odt = export_idt
target_bits = odt.bitwidth()
packed_bits = self.get_out_stream_width()
packed_bits = self.get_outstream_width()
out_npy_path = "{}/output.npy".format(code_gen_dir)
out_shape = self.get_folded_output_shape()
rtlsim_output_to_npy(
......
src/finn/custom_op/fpgadataflow/streamingmaxpool_batch.py
+ 10
− 10
View file @ 7f1d57ab
......@@ -84,14 +84,14 @@ class StreamingMaxPool_Batch(HLSCustomOp):
folded_oshape = self.get_folded_output_shape()
return np.prod(folded_oshape[:-1])
def get_in_stream_width(self):
def get_instream_width(self):
dt_bits = self.get_input_datatype().bitwidth()
ifm_ch = self.get_nodeattr("NumChannels")
return int(dt_bits * ifm_ch)
def get_out_stream_width(self):
def get_outstream_width(self):
"""For streaming maxpool out stream with is the same as in stream width"""
return self.get_in_stream_width()
return self.get_instream_width()
def make_shape_compatible_op(self, model):
exp_ishape = self.get_normal_input_shape()
......@@ -171,7 +171,7 @@ class StreamingMaxPool_Batch(HLSCustomOp):
# use binary for bipolar storage
dtype = DataType.BINARY
elem_bits = dtype.bitwidth()
packed_bits = self.get_in_stream_width()
packed_bits = self.get_instream_width()
packed_hls_type = "ap_uint<%d>" % packed_bits
elem_hls_type = dtype.get_hls_datatype_str()
npy_type = "float"
......@@ -185,10 +185,10 @@ class StreamingMaxPool_Batch(HLSCustomOp):
def strm_decl(self):
self.code_gen_dict["$STREAMDECLARATIONS$"] = []
self.code_gen_dict["$STREAMDECLARATIONS$"].append(
'hls::stream<ap_uint<{}>> in0 ("in0");'.format(self.get_in_stream_width())
'hls::stream<ap_uint<{}>> in0 ("in0");'.format(self.get_instream_width())
)
self.code_gen_dict["$STREAMDECLARATIONS$"].append(
'hls::stream<ap_uint<{}>> out ("out");'.format(self.get_out_stream_width())
'hls::stream<ap_uint<{}>> out ("out");'.format(self.get_outstream_width())
)
def docompute(self):
......@@ -215,7 +215,7 @@ class StreamingMaxPool_Batch(HLSCustomOp):
# use binary for bipolar storage
dtype = DataType.BINARY
elem_bits = dtype.bitwidth()
packed_bits = self.get_out_stream_width()
packed_bits = self.get_outstream_width()
packed_hls_type = "ap_uint<%d>" % packed_bits
elem_hls_type = dtype.get_hls_datatype_str()
npy_type = "float"
......@@ -239,7 +239,7 @@ class StreamingMaxPool_Batch(HLSCustomOp):
self.code_gen_dict["$SAVEASCNPY$"] = []
def blackboxfunction(self):
packed_bits = self.get_in_stream_width()
packed_bits = self.get_instream_width()
packed_hls_type = "ap_uint<%d>" % packed_bits
self.code_gen_dict["$BLACKBOXFUNCTION$"] = [
"void %s(hls::stream<%s > &in0, hls::stream<%s > &out)"
......@@ -307,7 +307,7 @@ class StreamingMaxPool_Batch(HLSCustomOp):
code_gen_dir, node.name, prefixed_top_name
)
if os.path.isfile(verilog_file):
nbits = self.get_in_stream_width()
nbits = self.get_instream_width()
rtlsim_inp = npy_to_rtlsim_input(
"{}/input_0.npy".format(code_gen_dir), export_idt, nbits
)
......@@ -324,7 +324,7 @@ class StreamingMaxPool_Batch(HLSCustomOp):
rtlsim_output = self.rtlsim(sim, rtlsim_inp)
odt = export_idt
target_bits = odt.bitwidth()
packed_bits = self.get_out_stream_width()
packed_bits = self.get_outstream_width()
out_npy_path = "{}/output.npy".format(code_gen_dir)
out_shape = self.get_folded_output_shape()
rtlsim_output_to_npy(
......
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