Merge pull request #186 from quetric/feature_hdl_intf_names

Added explicit naming of HDL interfaces, for use during ip stitching

src/finn/custom_op/fpgadataflow/__init__.py

@@ -102,6 +102,23 @@ class HLSCustomOp(CustomOp):
         prefixed_top_name = "%s_%s" % (node.name, node.name)
         return prefixed_top_name
 
+    def get_verilog_top_module_intf_names(self):
+        """Return a dict of names of input and output interfaces.
+        The keys reflect the protocols each interface implements:
+        'clk', 'rst', 'm_axis', 's_axis', 'aximm', 'axilite'.
+        Values are lists of names:
+        's_axis' names correspond to the list of node inputs in order,
+        'm_axis' names correspond to the list of node outputs in order'
+        Each block must have at most one aximm and one axilite."""
+        intf_names = {}
+        intf_names["clk"] = ["ap_clk"]
+        intf_names["rst"] = ["ap_rst_n"]
+        intf_names["s_axis"] = ["in0_V_V"]
+        intf_names["m_axis"] = ["out_V_V"]
+        intf_names["aximm"] = []
+        intf_names["axilite"] = []
+        return intf_names
+
     def get_verilog_top_filename(self):
         "Return the Verilog top module filename for this node."
 

src/finn/custom_op/fpgadataflow/addstreams_batch.py

@@ -356,3 +356,8 @@ class AddStreams_Batch(HLSCustomOp):
         self.code_gen_dict["$PRAGMAS$"].append(
             "#pragma HLS INTERFACE ap_ctrl_none port=return"
         )
+
+    def get_verilog_top_module_intf_names(self):
+        intf_names = super().get_verilog_top_module_intf_names()
+        intf_names["s_axis"] = ["in0_V_V", "in1_V_V"]
+        return intf_names

src/finn/custom_op/fpgadataflow/iodma.py

@@ -344,3 +344,15 @@ class IODMA(HLSCustomOp):
 
     def strm_decl(self):
         pass
+
+    def get_verilog_top_module_intf_names(self):
+        intf_names = super().get_verilog_top_module_intf_names()
+        if self.get_nodeattr("direction") == "out":
+            intf_names["s_axis"] = ["in0_V_V"]
+            intf_names["m_axis"] = []
+        else:
+            intf_names["s_axis"] = []
+            intf_names["m_axis"] = ["out_V_V"]
+        intf_names["axilite"] = ["s_axi_control"]
+        intf_names["aximm"] = ["m_axi_gmem"]
+        return intf_names

src/finn/custom_op/fpgadataflow/tlastmarker.py

@@ -33,8 +33,9 @@ class TLastMarker(HLSCustomOp):
     """Node that adds/removes AXI stream TLAST signals where needed. Its behavior
     is transparent in node-by-node execution, only visible in IP-stitched rtlsim or
     actual hardware.
-    This node  may be needed at the end of the network to signal a DMA write (needed by the
-    FINN PYNQ shell) or at the beginning to remove the end-of-burst from DMA read."""
+    This node  may be needed at the end of the network to signal a DMA write
+    (needed by the FINN PYNQ shell) or at the beginning to remove the end-of-burst
+    from DMA read."""
 
     def __init__(self, onnx_node):
         super().__init__(onnx_node)
@@ -239,3 +240,15 @@ class TLastMarker(HLSCustomOp):
         self.code_gen_dict["$STREAMDECLARATIONS$"].append(
             'hls::stream<OutDType> out ("out");'
         )
+
+    def get_verilog_top_module_intf_names(self):
+        intf_names = super().get_verilog_top_module_intf_names()
+        if self.get_nodeattr("Direction") == "in":
+            intf_names["s_axis"] = ["in0"]
+            intf_names["m_axis"] = ["out_V_V"]
+        else:
+            intf_names["s_axis"] = ["in0_V_V"]
+            intf_names["m_axis"] = ["out_r"]
+        if self.get_nodeattr("DynIters") == 1:
+            intf_names["axilite"] = ["s_axi_control"]
+        return intf_names