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Commit 5d0da833 authored by Thomas B. Preußer's avatar Thomas B. Preußer
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axi_info read not to block upon out-of-bounds accesses.

parent b2eca221
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...@@ -98,29 +98,21 @@ module axi_info #( ...@@ -98,29 +98,21 @@ module axi_info #(
if(1) begin : blkRead if(1) begin : blkRead
logic RValid = 0; logic RValid = 0;
logic [S_AXI_DATA_WIDTH-1:0] RData;// = 'x; logic [S_AXI_DATA_WIDTH-1:0] RData;// = 'x;
logic [ 1:0] RResp;// = 'x;
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if(rst) begin if(rst) begin
RValid <= 0; RValid <= 0;
RData <= 'x; RData <= 'x;
RResp <= 'x;
end end
else if(s_axi_ARREADY) begin else if(s_axi_ARREADY) begin
automatic logic [$left(s_axi_ARADDR):2] addr_eff = s_axi_ARADDR[$left(s_axi_ARADDR):2];
RValid <= s_axi_ARVALID; RValid <= s_axi_ARVALID;
if(s_axi_ARADDR < N) begin RData <= (addr_eff < N)? DATA[addr_eff] : 32'hDEADDEAD;
RData <= DATA[s_axi_ARADDR[$left(s_axi_ARADDR):2]];
RResp <= '0; // OKAY
end
else begin
RData <= 'x;
RResp <= '1; // DECERR
end
end end
end end
assign s_axi_ARREADY = !RValid || s_axi_RREADY; assign s_axi_ARREADY = !RValid || s_axi_RREADY;
assign s_axi_RVALID = RValid; assign s_axi_RVALID = RValid;
assign s_axi_RDATA = RData; assign s_axi_RDATA = RData;
assign s_axi_RRESP = RResp; assign s_axi_RRESP = '0; // OKAY
end : blkRead end : blkRead
......
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