[Test] add slow marker to most slow-running tests

tests/end2end/test_end2end_cnv_w1a1.py

@@ -167,6 +167,7 @@ def test_end2end_cnv_w1a1_fold_and_tlastmarker():
     model.save(build_dir + "/end2end_cnv_w1a1_folded.onnx")
 
 
+@pytest.mark.slow
 def test_end2end_cnv_w1a1_gen_hls_ip():
     model = ModelWrapper(build_dir + "/end2end_cnv_w1a1_folded.onnx")
     model = model.transform(PrepareIP(test_fpga_part, target_clk_ns))
@@ -263,6 +264,7 @@ def test_end2end_cnv_w1a1_make_pynq_proj():
     model.save(build_dir + "/end2end_cnv_w1a1_pynq_project.onnx")
 
 
+@pytest.mark.slow
 def test_end2end_cnv_w1a1_synth_pynq_project():
     model = ModelWrapper(build_dir + "/end2end_cnv_w1a1_pynq_project.onnx")
     model = model.transform(SynthPYNQProject())

tests/end2end/test_end2end_tfc_w1a1_throughput_test.py

@@ -153,6 +153,7 @@ def test_end2end_tfc_w1a1_fold_and_tlastmarker():
     model.save(build_dir + "/end2end_tfc_w1a1_folded.onnx")
 
 
+@pytest.mark.slow
 def test_end2end_tfc_w1a1_gen_hls_ip():
     model = ModelWrapper(build_dir + "/end2end_tfc_w1a1_folded.onnx")
     model = model.transform(PrepareIP(test_fpga_part, target_clk_ns))
@@ -241,6 +242,7 @@ def test_end2end_tfc_w1a1_make_pynq_proj():
     model.save(build_dir + "/end2end_tfc_w1a1_pynq_project.onnx")
 
 
+@pytest.mark.slow
 def test_end2end_tfc_w1a1_synth_pynq_project():
     model = ModelWrapper(build_dir + "/end2end_tfc_w1a1_pynq_project.onnx")
     model = model.transform(SynthPYNQProject())

tests/end2end/test_end2end_tfc_w1a2.py

@@ -145,6 +145,7 @@ def test_end2end_tfc_w1a2_fold_and_tlastmarker():
     model.save(build_dir + "/end2end_tfc_w1a2_folded.onnx")
 
 
+@pytest.mark.slow
 def test_end2end_tfc_w1a2_gen_hls_ip():
     model = ModelWrapper(build_dir + "/end2end_tfc_w1a2_folded.onnx")
     model = model.transform(PrepareIP(test_fpga_part, target_clk_ns))
@@ -233,6 +234,7 @@ def test_end2end_tfc_w1a2_make_pynq_proj():
     model.save(build_dir + "/end2end_tfc_w1a2_pynq_project.onnx")
 
 
+@pytest.mark.slow
 def test_end2end_tfc_w1a2_synth_pynq_project():
     model = ModelWrapper(build_dir + "/end2end_tfc_w1a2_pynq_project.onnx")
     model = model.transform(SynthPYNQProject())

tests/end2end/test_end2end_tfc_w2a2.py

@@ -145,6 +145,7 @@ def test_end2end_tfc_w2a2_fold_and_tlastmarker():
     model.save(build_dir + "/end2end_tfc_w2a2_folded.onnx")
 
 
+@pytest.mark.slow
 def test_end2end_tfc_w2a2_gen_hls_ip():
     model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_folded.onnx")
     model = model.transform(PrepareIP(test_fpga_part, target_clk_ns))
@@ -233,6 +234,7 @@ def test_end2end_tfc_w2a2_make_pynq_proj():
     model.save(build_dir + "/end2end_tfc_w2a2_pynq_project.onnx")
 
 
+@pytest.mark.slow
 def test_end2end_tfc_w2a2_synth_pynq_project():
     model = ModelWrapper(build_dir + "/end2end_tfc_w2a2_pynq_project.onnx")
     model = model.transform(SynthPYNQProject())

tests/fpgadataflow/test_fpgadataflow_convinputgenerator.py

@@ -137,6 +137,7 @@ def prepare_inputs(input_tensor):
 @pytest.mark.parametrize("exec_mode", ["cppsim", "rtlsim"])
 # input channel parallelism ("SIMD")
 @pytest.mark.parametrize("simd", [1, 2])
+@pytest.mark.slow
 def test_fpgadataflow_slidingwindow(idt, k, ifm_dim, ifm_ch, stride, exec_mode, simd):
     ofm_dim = int(((ifm_dim - k) / stride) + 1)
 

tests/fpgadataflow/test_fpgadataflow_dwc.py

@@ -55,6 +55,7 @@ def prepare_inputs(input_tensor, dt):
 @pytest.mark.parametrize("OUTWidth", [2, 4])
 # finn_dtype
 @pytest.mark.parametrize("finn_dtype", [DataType.BIPOLAR, DataType.INT2])
+@pytest.mark.slow
 def test_fpgadataflow_dwc_rtlsim(Shape, INWidth, OUTWidth, finn_dtype):
 
     # generate input data

tests/fpgadataflow/test_fpgadataflow_fclayer.py

@@ -149,6 +149,7 @@ def prepare_inputs(input_tensor, idt, wdt):
 @pytest.mark.parametrize("mw", [16])
 # HLS matrix height (output features)
 @pytest.mark.parametrize("mh", [16])
+@pytest.mark.slow
 def test_fpgadataflow_fclayer_cppsim(mem_mode, idt, wdt, act, nf, sf, mw, mh):
     if nf == -1:
         nf = mh
@@ -234,6 +235,7 @@ def test_fpgadataflow_fclayer_cppsim(mem_mode, idt, wdt, act, nf, sf, mw, mh):
 @pytest.mark.parametrize("mw", [16])
 # HLS matrix height (output features)
 @pytest.mark.parametrize("mh", [16])
+@pytest.mark.slow
 def test_fpgadataflow_fclayer_rtlsim(mem_mode, idt, wdt, act, nf, sf, mw, mh):
     if nf == -1:
         nf = mh

tests/fpgadataflow/test_fpgadataflow_fifo.py

@@ -76,6 +76,7 @@ def prepare_inputs(input_tensor, dt):
 @pytest.mark.parametrize("depth", [16])
 # finn_dtype
 @pytest.mark.parametrize("finn_dtype", [DataType.BIPOLAR])  # , DataType.INT2])
+@pytest.mark.slow
 def test_fpgadataflow_fifo_rtlsim(Shape, folded_shape, depth, finn_dtype):
 
     # generate input data

tests/fpgadataflow/test_fpgadataflow_ip_stitch.py

@@ -284,6 +284,7 @@ def test_fpgadataflow_ipstitch_pynq_projgen():
     model.save(ip_stitch_model_dir + "/test_fpgadataflow_pynq_projgen.onnx")
 
 
+@pytest.mark.slow
 def test_fpgadataflow_ipstitch_pynq_synth():
     model = ModelWrapper(ip_stitch_model_dir + "/test_fpgadataflow_pynq_projgen.onnx")
     model = model.transform(SynthPYNQProject())

tests/fpgadataflow/test_layer_streaming_maxpool_batch.py

@@ -121,6 +121,7 @@ def prepare_inputs(input_tensor):
 @pytest.mark.parametrize("ifm_ch", [1, 2])  # , 2, 3, 4])
 # execution mode
 @pytest.mark.parametrize("exec_mode", ["rtlsim", "cppsim"])
+@pytest.mark.slow
 def test_fpgadataflow_streamingmaxpool(idt, k, ifm_dim, ifm_ch, exec_mode):
     stride = k
     ofm_dim = int(((ifm_dim - k) / stride) + 1)